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[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension 

This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
	TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
	RGSR_EL1 and GCR_EL1.
	(aarch64_sys_reg_supported_p): New check for above.
	(aarch64_pstatefields): New entry for TCO.
	(aarch64_pstatefield_supported_p): New check for above.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
	TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
	GCR_EL1 MSR and MRS.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This commit is contained in:
Sudakshina Das 2018-11-12 13:26:01 +00:00
parent 503ba60025
commit 70f3d23af7
6 changed files with 110 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gas/ChangeLog
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@ -1,3 +1,11 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for

21
gas/testsuite/gas/aarch64/illegal-sysreg-4.l
View File

@ -14,3 +14,24 @@
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el3'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'id_pfr2_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsre0_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el3'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tco'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsre0_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el3'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'tfsr_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'

21
gas/testsuite/gas/aarch64/sysreg-4.d
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@ -1,5 +1,5 @@
#source: sysreg-4.s
#as: -march=armv8.5-a+rng
#as: -march=armv8.5-a+rng+memtag
#objdump: -dr
.*: file format .*
@ -19,3 +19,22 @@ Disassembly of section \.text:
.*: d53ed0e7 mrs x7, scxtnum_el3
.*: d53dd0e7 mrs x7, scxtnum_el12
.*: d5380388 mrs x8, id_pfr2_el1
.*: d53b42e1 mrs x1, tco
.*: d53b42e2 mrs x2, tco
.*: d5386621 mrs x1, tfsre0_el1
.*: d5386501 mrs x1, tfsr_el1
.*: d53c6502 mrs x2, tfsr_el2
.*: d53e6603 mrs x3, tfsr_el3
.*: d53d660c mrs x12, tfsr_el12
.*: d53810a1 mrs x1, rgsr_el1
.*: d53810c3 mrs x3, gcr_el1
.*: d51b42e1 msr tco, x1
.*: d51b42e2 msr tco, x2
.*: d5186621 msr tfsre0_el1, x1
.*: d5186501 msr tfsr_el1, x1
.*: d51c6502 msr tfsr_el2, x2
.*: d51e6603 msr tfsr_el3, x3
.*: d51d660c msr tfsr_el12, x12
.*: d51810a1 msr rgsr_el1, x1
.*: d51810c3 msr gcr_el1, x3
.*: d503489f msr tco, #0x8

26
gas/testsuite/gas/aarch64/sysreg-4.s
View File

@ -12,3 +12,29 @@ func:
mrs x7, scxtnum_el3
mrs x7, scxtnum_el12
mrs x8, id_pfr2_el1
# ARMv8.5-a+memtag
# MRS (register)
mrs x1, tco
mrs x2, TCO
mrs x1, tfsre0_el1
mrs x1, TFSR_EL1
mrs x2, TFSR_EL2
mrs x3, TFSR_EL3
mrs x12, TFSR_EL12
mrs x1, rgsr_el1
mrs x3, gcr_el1
# MSR (register)
msr tco, x1
msr TCO, x2
msr tfsre0_el1, x1
msr TFSR_EL1, x1
msr TFSR_EL2, x2
msr TFSR_EL3, x3
msr TFSR_EL12, x12
msr rgsr_el1, x1
msr gcr_el1, x3
# MSR (immediate)
msr TCO, #8

9
opcodes/ChangeLog
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@ -1,3 +1,12 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.

26
opcodes/aarch64-opc.c
View File

@ -3929,6 +3929,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
{ "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
{ "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
{ "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
{ "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
{ "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
{ "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
{ "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
{ "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
{ "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
{ "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
@ -4392,6 +4400,18 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
return FALSE;
/* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
if ((reg->value == CPENC (3, 3, C4, C2, 7)
|| reg->value == CPENC (3, 0, C6, C6, 1)
|| reg->value == CPENC (3, 0, C6, C5, 0)
|| reg->value == CPENC (3, 4, C6, C5, 0)
|| reg->value == CPENC (3, 6, C6, C6, 0)
|| reg->value == CPENC (3, 5, C6, C6, 0)
|| reg->value == CPENC (3, 0, C1, C0, 5)
|| reg->value == CPENC (3, 0, C1, C0, 6))
&& !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
return FALSE;
return TRUE;
}
@ -4411,6 +4431,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
{ "uao", 0x03, F_ARCHEXT },
{ "ssbs", 0x19, F_ARCHEXT },
{ "dit", 0x1a, F_ARCHEXT },
{ "tco", 0x1c, F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@ -4441,6 +4462,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
return FALSE;
/* TCO. Values are from aarch64_pstatefields. */
if (reg->value == 0x1c
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
return FALSE;
return TRUE;
}