this is part of the binutils/gdb sparc disassembler merge
This commit is contained in:
Jim Kingdon
parent
f7ed13c7d5
commit
3ac166b105
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@ -1,29 +1,23 @@
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/* disassemble sparc instructions for objdump
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Copyright (C) 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
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/* Print SPARC instructions.
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Copyright 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
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This file is part of the binutils.
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The binutils are free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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The binutils are distributed in the hope that they will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with the binutils; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "bfd.h"
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#include "sysdep.h"
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#include <stdio.h>
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#include "opcode/sparc.h"
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#include "objdump.h"
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extern int print_address();
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#include "dis-asm.h"
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#include <string.h>
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static char *reg_names[] =
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{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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@ -38,34 +32,37 @@ static char *reg_names[] =
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#define freg_names (®_names[4 * 8])
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/* FIXME--need to deal with byte order (probably using masking and
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shifting rather than bitfields is easiest). */
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union sparc_insn
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{
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unsigned long int code;
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struct
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{
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unsigned int _OP:2;
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#define op ldst._OP
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unsigned int _RD:5;
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#define rd ldst._RD
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unsigned int anop:2;
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#define op ldst.anop
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unsigned int anrd:5;
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#define rd ldst.anrd
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unsigned int op3:6;
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unsigned int _RS1:5;
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#define rs1 ldst._RS1
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unsigned int anrs1:5;
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#define rs1 ldst.anrs1
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unsigned int i:1;
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unsigned int _ASI:8;
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#define asi ldst._ASI
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unsigned int _RS2:5;
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#define rs2 ldst._RS2
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unsigned int anasi:8;
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#define asi ldst.anasi
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unsigned int anrs2:5;
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#define rs2 ldst.anrs2
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#define shcnt rs2
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} ldst;
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struct
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{
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unsigned int _OP:2, _RD:5, op3:6, _RS1:5, i:1;
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unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
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unsigned int IMM13:13;
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#define imm13 IMM13.IMM13
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} IMM13;
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struct
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{
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unsigned int _OP:2;
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unsigned int anop:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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@ -94,9 +91,9 @@ union sparc_insn
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#define imm22 disp22
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struct
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{
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unsigned int _OP:2;
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unsigned int _DISP30:30;
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#define disp30 call._DISP30
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unsigned int anop:2;
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unsigned int adisp30:30;
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#define disp30 call.adisp30
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} call;
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};
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@ -111,23 +108,28 @@ is_delayed_branch (insn)
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{
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const struct sparc_opcode *opcode = &sparc_opcodes[i];
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if ((opcode->match & insn.code) == opcode->match
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&& (opcode->lose & insn.code) == 0
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&& (opcode->flags&F_DELAYED))
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return 1;
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&& (opcode->lose & insn.code) == 0)
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return (opcode->flags & F_DELAYED);
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}
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return 0;
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}
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static int opcodes_sorted = 0;
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extern void qsort ();
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/* Print one instruction from MEMADDR on STREAM. */
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/* Print one instruction from MEMADDR on STREAM.
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We suffix the instruction with a comment that gives the absolute
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address involved, as well as its symbolic form, if the instruction
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is preceded by a findable `sethi' and it either adds an immediate
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displacement to that register, or it is an `add' or `or' instruction
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on that register. */
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int
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print_insn_sparc (memaddr, buffer, stream)
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print_insn_sparc (memaddr, info)
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bfd_vma memaddr;
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bfd_byte *buffer;
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FILE *stream;
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disassemble_info *info;
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{
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FILE *stream = info->stream;
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union sparc_insn insn;
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register unsigned int i;
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@ -140,7 +142,15 @@ print_insn_sparc (memaddr, buffer, stream)
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opcodes_sorted = 1;
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}
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memcpy(&insn,buffer, sizeof (insn));
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{
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int status =
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(*info->read_memory_func) (memaddr, (char *) &insn, sizeof (insn), info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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}
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for (i = 0; i < NUMOPCODES; ++i)
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{
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@ -156,48 +166,44 @@ memcpy(&insn,buffer, sizeof (insn));
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field of the opcode table. */
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int found_plus = 0;
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/* Do we have an 'or' instruction where rs1 is the same
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/* Do we have an `add' or `or' instruction where rs1 is the same
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as rsd, and which has the i bit set? */
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if (opcode->match == 0x80102000
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if ((opcode->match == 0x80102000 || opcode->match == 0x80002000)
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/* (or) (add) */
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&& insn.rs1 == insn.rd)
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imm_added_to_rs1 = 1;
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if (strchr (opcode->args, 'S') != 0)
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/* Reject the special case for `set'.
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The real `sethi' will match. */
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continue;
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if (insn.rs1 != insn.rd
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&& strchr (opcode->args, 'r') != 0)
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/* Can't do simple format if source and dest are different. */
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continue;
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fputs (opcode->name, stream);
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(*info->fprintf_func) (stream, opcode->name);
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{
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register const char *s;
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if (opcode->args[0] != ',')
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fputs (" ", stream);
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(*info->fprintf_func) (stream, " ");
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for (s = opcode->args; *s != '\0'; ++s)
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{
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while (*s == ',')
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{
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fputs (",", stream);
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(*info->fprintf_func) (stream, ",");
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++s;
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switch (*s) {
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case 'a':
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fputs ("a", stream);
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(*info->fprintf_func) (stream, "a");
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++s;
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continue;
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#ifndef NO_V9
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case 'N':
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fputs("pn", stream);
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(*info->fprintf_func) (stream, "pn");
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++s;
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continue;
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case 'T':
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fputs("pt", stream);
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(*info->fprintf_func) (stream, "pt");
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++s;
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continue;
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#endif /* NO_V9 */
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@ -207,7 +213,7 @@ memcpy(&insn,buffer, sizeof (insn));
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} /* switch on arg */
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} /* while there are comma started args */
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fputs (" ", stream);
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(*info->fprintf_func) (stream, " ");
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switch (*s)
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{
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@ -216,14 +222,14 @@ memcpy(&insn,buffer, sizeof (insn));
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/* note fall-through */
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default:
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fprintf (stream, "%c", *s);
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(*info->fprintf_func) (stream, "%c", *s);
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break;
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case '#':
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fputs ("0", stream);
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(*info->fprintf_func) (stream, "0");
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break;
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#define reg(n) fprintf (stream, "%%%s", reg_names[n])
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#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
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case '1':
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case 'r':
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reg (insn.rs1);
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@ -238,7 +244,7 @@ memcpy(&insn,buffer, sizeof (insn));
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break;
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#undef reg
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#define freg(n) fprintf (stream, "%%%s", freg_names[n])
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#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
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case 'e':
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case 'v': /* double/even */
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case 'V': /* quad/multiple of 4 */
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@ -258,7 +264,7 @@ memcpy(&insn,buffer, sizeof (insn));
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break;
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#undef freg
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#define creg(n) fprintf (stream, "%%c%u", (unsigned int) (n))
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#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
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case 'b':
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creg (insn.rs1);
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break;
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@ -273,8 +279,8 @@ memcpy(&insn,buffer, sizeof (insn));
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#undef creg
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case 'h':
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fprintf (stream, "%%hi(%#x)",
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(unsigned int) insn.imm22 << 10);
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(*info->fprintf_func) (stream, "%%hi(%#x)",
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(int) insn.imm22 << 10);
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break;
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case 'i':
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@ -285,7 +291,7 @@ memcpy(&insn,buffer, sizeof (insn));
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/* Check to see whether we have a 1+i, and take
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note of that fact.
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Note: because of the way we sort the table,
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we will be matching 1+i rather than i+1,
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so it is OK to assume that i is after +,
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@ -294,9 +300,9 @@ memcpy(&insn,buffer, sizeof (insn));
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imm_added_to_rs1 = 1;
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if (imm <= 9)
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fprintf (stream, "%d", imm);
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(*info->fprintf_func) (stream, "%d", imm);
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else
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fprintf (stream, "%#x", (unsigned) imm);
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(*info->fprintf_func) (stream, "%#x", imm);
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}
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break;
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@ -324,9 +330,9 @@ memcpy(&insn,buffer, sizeof (insn));
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imm_added_to_rs1 = 1;
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if (imm <= 9)
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fprintf (stream, "%d", imm);
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(info->fprintf_func) (stream, "%d", imm);
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else
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fprintf (stream, "%#x", (unsigned) imm);
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(info->fprintf_func) (stream, "%#x", (unsigned) imm);
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}
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break;
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@ -389,8 +395,9 @@ memcpy(&insn,buffer, sizeof (insn));
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if ((insn.code >> 22) == 0)
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/* Special case for `unimp'. Don't try to turn
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it's operand into a function offset. */
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fprintf (stream, "%#x",
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(unsigned) (((int) insn.disp22 << 10) >> 10));
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(*info->fprintf_func)
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(stream, "%#x",
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(int) (((int) insn.disp22 << 10) >> 10));
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else
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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@ -401,39 +408,39 @@ memcpy(&insn,buffer, sizeof (insn));
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break;
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case 'A':
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fprintf (stream, "(%d)", (int) insn.asi);
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(*info->fprintf_func) (stream, "(%d)", (int) insn.asi);
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break;
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case 'C':
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fputs ("%csr", stream);
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(*info->fprintf_func) (stream, "%csr");
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break;
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case 'F':
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fputs ("%fsr", stream);
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(*info->fprintf_func) (stream, "%fsr");
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break;
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case 'p':
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fputs ("%psr", stream);
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(*info->fprintf_func) (stream, "%psr");
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break;
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case 'q':
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fputs ("%fq", stream);
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(*info->fprintf_func) (stream, "%fq");
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break;
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case 'Q':
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fputs ("%cq", stream);
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(*info->fprintf_func) (stream, "%cq");
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break;
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case 't':
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fputs ("%tbr", stream);
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(*info->fprintf_func) (stream, "%tbr");
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break;
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case 'w':
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fputs ("%wim", stream);
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(*info->fprintf_func) (stream, "%wim");
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break;
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case 'y':
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fputs ("%y", stream);
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(*info->fprintf_func) (stream, "%y");
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break;
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}
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}
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@ -448,9 +455,12 @@ memcpy(&insn,buffer, sizeof (insn));
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if (imm_added_to_rs1)
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{
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union sparc_insn prev_insn;
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int errcode = 0;
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int errcode;
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memcpy(&prev_insn, buffer -4, sizeof (prev_insn));
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errcode =
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(*info->read_memory_func)
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(memaddr - 4,
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(char *)&prev_insn, sizeof (prev_insn));
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if (errcode == 0)
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{
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@ -464,8 +474,8 @@ memcpy(&insn,buffer, sizeof (insn));
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*/
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if (is_delayed_branch (prev_insn))
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memcpy(&prev_insn, buffer - 8, sizeof(prev_insn));
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errcode = (*info->read_memory_func)
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(memaddr - 8, (char *)&prev_insn, sizeof (prev_insn));
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}
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/* If there was a problem reading memory, then assume
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@ -476,7 +486,7 @@ memcpy(&insn,buffer, sizeof (insn));
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if ((prev_insn.code & 0xc1c00000) == 0x01000000
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&& prev_insn.rd == insn.rs1)
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{
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fprintf (stream, "\t! ");
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(*info->fprintf_func) (stream, "\t! ");
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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print_address (((int) prev_insn.imm22 << 10)
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@ -489,11 +499,10 @@ memcpy(&insn,buffer, sizeof (insn));
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}
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}
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fprintf (stream, "%#8x", insn.code);
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(*info->fprintf_func) (stream, "%#8x", insn.code);
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return sizeof (insn);
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}
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/* Compare opcodes A and B. */
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static int
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@ -548,6 +557,27 @@ compare_opcodes (a, b)
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/* They are functionally equal. So as long as the opcode table is
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valid, we can put whichever one first we want, on aesthetic grounds. */
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/* Our first aesthetic ground is that aliases defer to real insns. */
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{
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int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
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if (alias_diff != 0)
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/* Put the one that isn't an alias first. */
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return alias_diff;
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}
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/* Except for aliases, two "identical" instructions had
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better have the same opcode. This is a sanity check on the table. */
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i = strcmp (op0->name, op1->name);
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if (i)
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if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
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return i;
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else
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fprintf (stderr,
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"Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
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op0->name, op1->name);
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/* Fewer arguments are preferred. */
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{
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int length_diff = strlen (op0->args) - strlen (op1->args);
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if (length_diff != 0)
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