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[binutils][aarch64] New iclass sve_size_hsd2. 

Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_hsd2 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_hsd2 iclass decode.
	* aarch64-opc.c (fields): Handle SVE_size field.
	* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
This commit is contained in:
Matthew Malcomson 2019-05-09 10:29:16 +01:00
parent adccc50753
commit 3bd82c86f0
7 changed files with 28 additions and 0 deletions
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4
include/ChangeLog
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@ -1,3 +1,7 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.

1
include/opcode/aarch64.h
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@ -590,6 +590,7 @@ enum aarch64_insn_class
sve_size_bhs,
sve_size_bhsd,
sve_size_hsd,
sve_size_hsd2,
sve_size_sd,
testbranch,
cryptosm3,

9
opcodes/ChangeLog
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@ -1,3 +1,12 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_hsd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_hsd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_size field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.

5
opcodes/aarch64-asm.c
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@ -1659,6 +1659,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
break;
case sve_size_hsd2:
insert_field (FLD_SVE_size, &inst->value,
aarch64_get_variant (inst) + 1, 0);
break;
default:
break;
}

7
opcodes/aarch64-dis.c
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@ -2810,6 +2810,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = extract_field (FLD_SVE_sz, inst->value, 0);
break;
case sve_size_hsd2:
i = extract_field (FLD_SVE_size, inst->value, 0);
if (i < 1)
return FALSE;
variant = i - 1;
break;
default:
/* No mapping between instruction class and qualifiers. */
return TRUE;

1
opcodes/aarch64-opc.c
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@ -311,6 +311,7 @@ const aarch64_field fields[] =
{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
{ 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */

1
opcodes/aarch64-opc.h
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@ -138,6 +138,7 @@ enum aarch64_field_kind
FLD_SVE_rot2,
FLD_SVE_rot3,
FLD_SVE_sz,
FLD_SVE_size,
FLD_SVE_tsz,
FLD_SVE_tszh,
FLD_SVE_tszl_8,