[binutils][aarch64] New iclass sve_size_hsd2.
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
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@ -1,3 +1,7 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
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@ -590,6 +590,7 @@ enum aarch64_insn_class
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sve_size_bhs,
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sve_size_bhsd,
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sve_size_hsd,
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sve_size_hsd2,
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sve_size_sd,
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testbranch,
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cryptosm3,
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@ -1,3 +1,12 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
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sve_size_hsd2 iclass encode.
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* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
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sve_size_hsd2 iclass decode.
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* aarch64-opc.c (fields): Handle SVE_size field.
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* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm-2.c: Regenerated.
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@ -1659,6 +1659,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
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insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
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break;
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case sve_size_hsd2:
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insert_field (FLD_SVE_size, &inst->value,
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aarch64_get_variant (inst) + 1, 0);
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break;
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default:
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break;
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}
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@ -2810,6 +2810,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
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variant = extract_field (FLD_SVE_sz, inst->value, 0);
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break;
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case sve_size_hsd2:
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i = extract_field (FLD_SVE_size, inst->value, 0);
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if (i < 1)
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return FALSE;
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variant = i - 1;
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break;
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default:
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/* No mapping between instruction class and qualifiers. */
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return TRUE;
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@ -311,6 +311,7 @@ const aarch64_field fields[] =
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{ 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
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{ 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
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{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
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{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
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{ 16, 4 }, /* SVE_tsz: triangular size select. */
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{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
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{ 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
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@ -138,6 +138,7 @@ enum aarch64_field_kind
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FLD_SVE_rot2,
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FLD_SVE_rot3,
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FLD_SVE_sz,
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FLD_SVE_size,
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FLD_SVE_tsz,
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FLD_SVE_tszh,
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FLD_SVE_tszl_8,
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