x86: drop/replace IgnoreSize

Even after commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
  skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.

To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.

Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.

Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.

Convert VexW= again to their respective VexW* on lines touched anyway.

gas/ChangeLog

@@ -1,3 +1,10 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+	* config/tc-i386.c (match_template): Extend code in logic
+	rejecting certain suffixes in certain modes to also cover mask
+	register use and VecSIB. Drop special casing of broadcast. Skip
+	immediates in the check.
+
 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (match_template): Fold duplicate code in

gas/config/tc-i386.c

@@ -5877,6 +5877,7 @@ match_template (char mnem_suffix)
       /* In general, don't allow
 	 - 64-bit operands outside of 64-bit mode,
 	 - 32-bit operands on pre-386.  */
+      j = i.imm_operands + (t->operands > i.imm_operands + 1);
       if (((i.suffix == QWORD_MNEM_SUFFIX
 	    && flag_code != CODE_64BIT
 	    && (t->base_opcode != 0x0fc7
@@ -5885,13 +5886,16 @@ match_template (char mnem_suffix)
 	       && !cpu_arch_flags.bitfield.cpui386))
 	  && (intel_syntax
 	      ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
-		 && !t->opcode_modifier.broadcast
 		 && !intel_float_operand (t->name))
 	      : intel_float_operand (t->name) != 2)
-	  && ((operand_types[0].bitfield.class != RegMMX
-	       && operand_types[0].bitfield.class != RegSIMD)
-	      || (operand_types[t->operands > 1].bitfield.class != RegMMX
-		  && operand_types[t->operands > 1].bitfield.class != RegSIMD)))
+	  && (t->operands == i.imm_operands
+	      || (operand_types[i.imm_operands].bitfield.class != RegMMX
+	       && operand_types[i.imm_operands].bitfield.class != RegSIMD
+	       && operand_types[i.imm_operands].bitfield.class != RegMask)
+	      || (operand_types[j].bitfield.class != RegMMX
+		  && operand_types[j].bitfield.class != RegSIMD
+		  && operand_types[j].bitfield.class != RegMask))
+	  && !t->opcode_modifier.vecsib)
 	continue;
 
       /* Do not verify operands when there are none.  */

opcodes/ChangeLog

@@ -1,3 +1,9 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
+	VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
+	* i386-tbl.h: Re-generate.
+
 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.