RISC-V: Support the read-only CSR checking.
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address is 0x3. The read-only CSR can not be written by the CSR instructions. gas/ * config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate we are assembling instruction with CSR. Call riscv_csr_read_only_check after parsing all arguments. (enum csr_insn_type): New enum is used to classify the CSR instruction. (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These are used to check if we write a read-only CSR by the CSR instruction. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test all CSR for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test all CSR instructions for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
This commit is contained in:
Nelson Chu
Jim Wilson
parent
2ca89224b1
commit
54b2aec10d
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@ -1,5 +1,20 @@
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2020-02-20 Nelson Chu <nelson.chu@sifive.com>
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* config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate
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we are assembling instruction with CSR. Call riscv_csr_read_only_check
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after parsing all arguments.
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(enum csr_insn_type): New enum is used to classify the CSR instruction.
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(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
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are used to check if we write a read-only CSR by the CSR instruction.
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* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
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all CSR for the read-only CSR checking.
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* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
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* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
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* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
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all CSR instructions for the read-only CSR checking.
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* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
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* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
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* config/tc-riscv.c (struct riscv_set_options): New field csr_check.
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(riscv_opts): Initialize it.
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(reg_lookup_internal): Check the `riscv_opts.csr_check`
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@ -1486,6 +1486,56 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
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return FALSE;
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}
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/* All RISC-V CSR instructions belong to one of these classes. */
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enum csr_insn_type
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{
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INSN_NOT_CSR,
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INSN_CSRRW,
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INSN_CSRRS,
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INSN_CSRRC
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};
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/* Return which CSR instruction is checking. */
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static enum csr_insn_type
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riscv_csr_insn_type (insn_t insn)
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{
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if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
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|| ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
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return INSN_CSRRW;
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else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
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|| ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
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return INSN_CSRRS;
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else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
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|| ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
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return INSN_CSRRC;
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else
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return INSN_NOT_CSR;
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}
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/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
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CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
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CSR address is 0x3. */
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static bfd_boolean
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riscv_csr_read_only_check (insn_t insn)
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{
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int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
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int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
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int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
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enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
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if (readonly
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&& (((csr_insn == INSN_CSRRS
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|| csr_insn == INSN_CSRRC)
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&& rs1 != 0)
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|| csr_insn == INSN_CSRRW))
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return FALSE;
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return TRUE;
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}
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/* This routine assembles an instruction into its binary format. As a
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side effect, it sets the global variable imm_reloc to the type of
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relocation to do if one of the operands is an address expression. */
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@ -1504,6 +1554,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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int argnum;
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const struct percent_op_match *p;
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const char *error = "unrecognized opcode";
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/* Indicate we are assembling instruction with CSR. */
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bfd_boolean insn_with_csr = FALSE;
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/* Parse the name of the instruction. Terminate the string if whitespace
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is found so that hash_find only sees the name part of the string. */
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@ -1550,11 +1602,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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: insn->match) == 2
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&& !riscv_opts.rvc)
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break;
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/* Check if we write a read-only CSR by the CSR
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instruction. */
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if (insn_with_csr
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&& riscv_opts.csr_check
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&& !riscv_csr_read_only_check (ip->insn_opcode))
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{
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/* Restore the character in advance, since we want to
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report the detailed warning message here. */
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if (save_c)
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*(argsStart - 1) = save_c;
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as_warn (_("Read-only CSR is written `%s'"), str);
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insn_with_csr = FALSE;
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}
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}
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if (*s != '\0')
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break;
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/* Successful assembly. */
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error = NULL;
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insn_with_csr = FALSE;
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goto out;
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case 'C': /* RVC */
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@ -1899,6 +1966,7 @@ rvc_lui:
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continue;
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case 'E': /* Control register. */
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insn_with_csr = TRUE;
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if (reg_lookup (&s, RCLASS_CSR, ®no))
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INSERT_OPERAND (CSR, *ip, regno);
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else
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@ -2219,6 +2287,7 @@ jump:
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}
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s = argsStart;
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error = _("illegal operands");
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insn_with_csr = FALSE;
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}
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out:
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@ -0,0 +1,3 @@
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#as: -march=rv32if -mcsr-check
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#source: priv-reg-fail-read-only-01.s
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#warning_output: priv-reg-fail-read-only-01.l
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@ -0,0 +1,69 @@
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.*Assembler messages:
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.*Warning: Read-only CSR is written `csrw cycle,a1'
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.*Warning: Read-only CSR is written `csrw time,a1'
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.*Warning: Read-only CSR is written `csrw instret,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter3,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter4,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter5,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter6,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter7,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter8,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter9,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter10,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter11,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter12,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter13,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter14,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter15,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter16,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter17,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter18,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter19,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter20,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter21,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter22,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter23,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter24,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter25,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter26,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter27,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter28,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter29,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter30,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter31,a1'
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.*Warning: Read-only CSR is written `csrw cycleh,a1'
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.*Warning: Read-only CSR is written `csrw timeh,a1'
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.*Warning: Read-only CSR is written `csrw instreth,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter3h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter4h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter5h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter6h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter7h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter8h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter9h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter10h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter11h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter12h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter13h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter14h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter15h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter16h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter17h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter18h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter19h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter20h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter21h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter22h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter23h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter24h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter25h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter26h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter27h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter28h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter29h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter30h,a1'
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.*Warning: Read-only CSR is written `csrw hpmcounter31h,a1'
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.*Warning: Read-only CSR is written `csrw mvendorid,a1'
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.*Warning: Read-only CSR is written `csrw marchid,a1'
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.*Warning: Read-only CSR is written `csrw mimpid,a1'
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.*Warning: Read-only CSR is written `csrw mhartid,a1'
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@ -0,0 +1,269 @@
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.macro csr val
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csrw \val, a1
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.endm
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# 1.9.1 registers
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csr ustatus
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csr uie
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csr utvec
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csr uscratch
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csr uepc
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csr ucause
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csr ubadaddr
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csr uip
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csr fflags
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csr frm
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csr fcsr
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csr cycle
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csr time
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csr instret
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csr hpmcounter3
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csr hpmcounter4
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csr hpmcounter5
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csr hpmcounter6
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csr hpmcounter7
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csr hpmcounter8
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csr hpmcounter9
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csr hpmcounter10
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csr hpmcounter11
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csr hpmcounter12
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csr hpmcounter13
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csr hpmcounter14
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csr hpmcounter15
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csr hpmcounter16
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csr hpmcounter17
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csr hpmcounter18
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csr hpmcounter19
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csr hpmcounter20
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csr hpmcounter21
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csr hpmcounter22
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csr hpmcounter23
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csr hpmcounter24
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csr hpmcounter25
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csr hpmcounter26
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csr hpmcounter27
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csr hpmcounter28
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csr hpmcounter29
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csr hpmcounter30
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csr hpmcounter31
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csr cycleh
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csr timeh
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csr instreth
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csr hpmcounter3h
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csr hpmcounter4h
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csr hpmcounter5h
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csr hpmcounter6h
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csr hpmcounter7h
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csr hpmcounter8h
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csr hpmcounter9h
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csr hpmcounter10h
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csr hpmcounter11h
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csr hpmcounter12h
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csr hpmcounter13h
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csr hpmcounter14h
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csr hpmcounter15h
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csr hpmcounter16h
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csr hpmcounter17h
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csr hpmcounter18h
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csr hpmcounter19h
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csr hpmcounter20h
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csr hpmcounter21h
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csr hpmcounter22h
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csr hpmcounter23h
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csr hpmcounter24h
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csr hpmcounter25h
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csr hpmcounter26h
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csr hpmcounter27h
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csr hpmcounter28h
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csr hpmcounter29h
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csr hpmcounter30h
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csr hpmcounter31h
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csr sstatus
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csr sedeleg
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csr sideleg
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csr sie
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csr stvec
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csr sscratch
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csr sepc
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csr scause
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csr sbadaddr
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csr sip
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csr sptbr
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csr hstatus
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csr hedeleg
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csr hideleg
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csr hie
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csr htvec
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csr hscratch
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csr hepc
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csr hcause
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csr hbadaddr
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csr hip
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csr mvendorid
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csr marchid
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csr mimpid
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csr mhartid
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csr mstatus
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csr misa
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csr medeleg
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csr mideleg
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csr mie
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csr mtvec
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csr mscratch
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csr mepc
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csr mcause
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csr mbadaddr
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csr mip
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csr mbase
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csr mbound
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csr mibase
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csr mibound
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csr mdbase
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csr mdbound
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csr mcycle
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csr minstret
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csr mhpmcounter3
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csr mhpmcounter4
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csr mhpmcounter5
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csr mhpmcounter6
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csr mhpmcounter7
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csr mhpmcounter8
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csr mhpmcounter9
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csr mhpmcounter10
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csr mhpmcounter11
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csr mhpmcounter12
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csr mhpmcounter13
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csr mhpmcounter14
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csr mhpmcounter15
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csr mhpmcounter16
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csr mhpmcounter17
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csr mhpmcounter18
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csr mhpmcounter19
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csr mhpmcounter20
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csr mhpmcounter21
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csr mhpmcounter22
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csr mhpmcounter23
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csr mhpmcounter24
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csr mhpmcounter25
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csr mhpmcounter26
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csr mhpmcounter27
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csr mhpmcounter28
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csr mhpmcounter29
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csr mhpmcounter30
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csr mhpmcounter31
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csr mcycleh
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csr minstreth
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csr mhpmcounter3h
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csr mhpmcounter4h
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csr mhpmcounter5h
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csr mhpmcounter6h
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csr mhpmcounter7h
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csr mhpmcounter8h
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csr mhpmcounter9h
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csr mhpmcounter10h
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csr mhpmcounter11h
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csr mhpmcounter12h
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csr mhpmcounter13h
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csr mhpmcounter14h
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csr mhpmcounter15h
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csr mhpmcounter16h
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csr mhpmcounter17h
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csr mhpmcounter18h
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csr mhpmcounter19h
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csr mhpmcounter20h
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csr mhpmcounter21h
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csr mhpmcounter22h
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csr mhpmcounter23h
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csr mhpmcounter24h
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csr mhpmcounter25h
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csr mhpmcounter26h
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csr mhpmcounter27h
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csr mhpmcounter28h
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csr mhpmcounter29h
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csr mhpmcounter30h
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csr mhpmcounter31h
|
||||
|
||||
csr mucounteren
|
||||
csr mscounteren
|
||||
csr mhcounteren
|
||||
|
||||
csr mhpmevent3
|
||||
csr mhpmevent4
|
||||
csr mhpmevent5
|
||||
csr mhpmevent6
|
||||
csr mhpmevent7
|
||||
csr mhpmevent8
|
||||
csr mhpmevent9
|
||||
csr mhpmevent10
|
||||
csr mhpmevent11
|
||||
csr mhpmevent12
|
||||
csr mhpmevent13
|
||||
csr mhpmevent14
|
||||
csr mhpmevent15
|
||||
csr mhpmevent16
|
||||
csr mhpmevent17
|
||||
csr mhpmevent18
|
||||
csr mhpmevent19
|
||||
csr mhpmevent20
|
||||
csr mhpmevent21
|
||||
csr mhpmevent22
|
||||
csr mhpmevent23
|
||||
csr mhpmevent24
|
||||
csr mhpmevent25
|
||||
csr mhpmevent26
|
||||
csr mhpmevent27
|
||||
csr mhpmevent28
|
||||
csr mhpmevent29
|
||||
csr mhpmevent30
|
||||
csr mhpmevent31
|
||||
|
||||
csr tselect
|
||||
csr tdata1
|
||||
csr tdata2
|
||||
csr tdata3
|
||||
|
||||
csr dcsr
|
||||
csr dpc
|
||||
csr dscratch
|
||||
# 1.10 registers
|
||||
csr utval
|
||||
|
||||
csr scounteren
|
||||
csr stval
|
||||
csr satp
|
||||
|
||||
csr mcounteren
|
||||
csr mtval
|
||||
|
||||
csr pmpcfg0
|
||||
csr pmpcfg1
|
||||
csr pmpcfg2
|
||||
csr pmpcfg3
|
||||
csr pmpaddr0
|
||||
csr pmpaddr1
|
||||
csr pmpaddr2
|
||||
csr pmpaddr3
|
||||
csr pmpaddr4
|
||||
csr pmpaddr5
|
||||
csr pmpaddr6
|
||||
csr pmpaddr7
|
||||
csr pmpaddr8
|
||||
csr pmpaddr9
|
||||
csr pmpaddr10
|
||||
csr pmpaddr11
|
||||
csr pmpaddr12
|
||||
csr pmpaddr13
|
||||
csr pmpaddr14
|
||||
csr pmpaddr15
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=rv32if -mcsr-check
|
||||
#source: priv-reg-fail-read-only-02.s
|
||||
#warning_output: priv-reg-fail-read-only-02.l
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
.*Assembler messages:
|
||||
.*Warning: Read-only CSR is written `csrrw a0,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrrw a0,cycle,zero'
|
||||
.*Warning: Read-only CSR is written `csrrw zero,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrrw zero,cycle,zero'
|
||||
.*Warning: Read-only CSR is written `csrw cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrw cycle,zero'
|
||||
.*Warning: Read-only CSR is written `csrrwi a0,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrrwi a0,cycle,0x0'
|
||||
.*Warning: Read-only CSR is written `csrrwi zero,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrrwi zero,cycle,0x0'
|
||||
.*Warning: Read-only CSR is written `csrwi cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrwi cycle,0x0'
|
||||
.*Warning: Read-only CSR is written `csrrs a0,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrrs zero,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrs cycle,a0'
|
||||
.*Warning: Read-only CSR is written `csrrsi a0,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrrsi zero,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrsi cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrrc a0,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrrc zero,cycle,a1'
|
||||
.*Warning: Read-only CSR is written `csrc cycle,a0'
|
||||
.*Warning: Read-only CSR is written `csrrci a0,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrrci zero,cycle,0xb'
|
||||
.*Warning: Read-only CSR is written `csrci cycle,0xb'
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
# CSRRW and CSRRWI always write CSR
|
||||
# CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when rs isn't zero.
|
||||
|
||||
# csrrw rd, csr, rs
|
||||
csrrw a0, ustatus, a1
|
||||
csrrw a0, cycle, a1
|
||||
csrrw a0, cycle, zero
|
||||
csrrw zero, cycle, a1
|
||||
csrrw zero, cycle, zero
|
||||
fscsr a0, a1
|
||||
fsrm a0, a1
|
||||
fsflags a0, a1
|
||||
# csrrw zero, csr, rs
|
||||
csrw ustatus, a1
|
||||
csrw cycle, a1
|
||||
csrw cycle, zero
|
||||
fscsr a1
|
||||
fsrm a1
|
||||
fsflags a1
|
||||
# csrrwi rd, csr, imm
|
||||
csrrwi a0, ustatus, 0xb
|
||||
csrrwi a0, cycle, 0xb
|
||||
csrrwi a0, cycle, 0x0
|
||||
csrrwi zero, cycle, 0xb
|
||||
csrrwi zero, cycle, 0x0
|
||||
# csrrwi zero, csr, imm
|
||||
csrwi ustatus, 0xb
|
||||
csrwi cycle, 0xb
|
||||
csrwi cycle, 0x0
|
||||
|
||||
# csrrs rd, csr, rs
|
||||
csrrs a0, ustatus, a1
|
||||
csrrs a0, cycle, a1
|
||||
csrrs a0, cycle, zero
|
||||
csrrs zero, cycle, a1
|
||||
csrrs zero, cycle, zero
|
||||
# csrrs rd, csr, zero
|
||||
csrr a0, ustatus
|
||||
csrr a0, cycle
|
||||
csrr zero, cycle
|
||||
rdinstret a0
|
||||
rdinstret zero
|
||||
rdinstreth a0
|
||||
rdinstreth zero
|
||||
rdcycle a0
|
||||
rdcycle zero
|
||||
rdcycleh a0
|
||||
rdcycleh zero
|
||||
rdtime a0
|
||||
rdtime zero
|
||||
rdtimeh a0
|
||||
rdtimeh zero
|
||||
frcsr a0
|
||||
frrm a0
|
||||
frflags a0
|
||||
# csrrs zero, csr, rs
|
||||
csrs ustatus, a0
|
||||
csrs cycle, a0
|
||||
csrs cycle, zero
|
||||
# csrrsi rd, csr, imm
|
||||
csrrsi a0, ustatus, 0xb
|
||||
csrrsi a0, cycle, 0xb
|
||||
csrrsi a0, cycle, 0x0
|
||||
csrrsi zero, cycle, 0xb
|
||||
csrrsi zero, cycle, 0x0
|
||||
# csrrsi zero, csr, imm
|
||||
csrsi ustatus, 0xb
|
||||
csrsi cycle, 0xb
|
||||
csrsi cycle, 0x0
|
||||
|
||||
# csrrc a0, csr, a1
|
||||
csrrc a0, ustatus, a1
|
||||
csrrc a0, cycle, a1
|
||||
csrrc a0, cycle, zero
|
||||
csrrc zero, cycle, a1
|
||||
csrrc zero, cycle, zero
|
||||
# csrrc zero, csr, rs
|
||||
csrc ustatus, a0
|
||||
csrc cycle, a0
|
||||
csrc cycle, zero
|
||||
# csrrci rd, csr, imm
|
||||
csrrci a0, ustatus, 0xb
|
||||
csrrci a0, cycle, 0xb
|
||||
csrrci a0, cycle, 0x0
|
||||
csrrci zero, cycle, 0xb
|
||||
csrrci zero, cycle, 0x0
|
||||
# csrrci zero, csr, imm
|
||||
csrci ustatus, 0xb
|
||||
csrci cycle, 0xb
|
||||
csrci cycle, 0x0
|
||||
Loading…
Reference in New Issue