sim: cr16: convert to common sim memory modules
The cr16 port has a lot of translation/offset logic baked into it, but it all looks like copy & paste from the d10v port rather than something the cr16 port wants.
This commit is contained in:
Mike Frysinger
parent
267b3b8e06
commit
761e171ad8
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@ -1,3 +1,9 @@
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2015-11-15 Mike Frysinger <vapier@gentoo.org>
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* sim-cr16.h (SIM_CR16_MEMORY_UNIFIED, SIM_CR16_MEMORY_INSN,
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SIM_CR16_MEMORY_DATA, SIM_CR16_MEMORY_DMAP, SIM_CR16_MEMORY_IMAP):
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Delete.
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2015-11-14 Mike Frysinger <vapier@gentoo.org>
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* sim-arm.h: Delete __cplusplus checks and extern "C" linkage.
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@ -20,15 +20,6 @@
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#if !defined (SIM_CR16_H)
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#define SIM_CR16_H
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enum
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{
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SIM_CR16_MEMORY_UNIFIED = 0x00000000,
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SIM_CR16_MEMORY_INSN = 0x10000000,
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SIM_CR16_MEMORY_DATA = 0x10000000,
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SIM_CR16_MEMORY_DMAP = 0x10000000,
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SIM_CR16_MEMORY_IMAP = 0x10000000
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};
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/* The simulator makes use of the following register information. */
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enum sim_cr16_regs
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@ -1,3 +1,31 @@
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2015-11-15 Mike Frysinger <vapier@gentoo.org>
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* Makefile.in (SIM_OBJS): Delete endian.o.
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(INCLUDE): Delete endian.c.
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* configure.ac (SIM_AC_OPTION_ENDIAN): Declare little endian.
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(SIM_AC_OPTION_ALIGNMENT): release unaligned loads.
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* configure: Regenerate.
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* cr16_sim.h (IMAP_BLOCK_SIZE, DMAP_BLOCK_SIZE, SEGMENT_SIZE,
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IMEM_SEGMENTS, DMEM_SEGMENTS, UMEM_SEGMENTS, cr16_memory, dmem_addr,
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imem_addr, decode_pc, get_longword, get_word, write_word,
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write_longword, READ_16): Delete.
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(struct _state): Delete mem member.
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(endian.c): Delete include.
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(SB, RB, SW, RW, SLW): Rewrite to use sim-core functions.
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(get_longword): New function.
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(RLW): Rewrite to use get_longword.
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* endian.c: Delete file.
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* interp.c (map_memory, sim_size, last_segname, last_from, last_to,
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IMAP0_OFFSET, DMAP0_OFFSET, DMAP2_SHADDOW, DMAP2_OFFSET,
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dmap_register, imap_register, sim_cr16_translate_dmap_addr,
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sim_cr16_translate_imap_addr, sim_cr16_translate_addr, map_memory,
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xfer_mem, sim_write, sim_read, dmem_addr, imem_addr): Delete.
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(do_run): Delete iaddr and replace imem_addr/get_longword with RW.
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(sim_open): Call sim_do_commandf. Delete sim_size call.
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(sim_resume): Delete iaddr and replace imem_addr/get_longword with
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RLW.
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* simops.c (MEMPTR): Rewrite to use sim_core_trans_addr.
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2015-11-15 Mike Frysinger <vapier@gentoo.org>
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* cr16_sim.h (struct simops): Add SIM_DESC and SIM_CPU to func args.
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@ -23,11 +23,10 @@ SIM_OBJS = \
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sim-reg.o \
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interp.o \
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table.o \
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simops.o \
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endian.o
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simops.o
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SIM_EXTRA_CLEAN = clean-extra
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INCLUDE = cr16_sim.h $(srcroot)/include/gdb/callback.h targ-vals.h endian.c \
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INCLUDE = cr16_sim.h $(srcroot)/include/gdb/callback.h targ-vals.h \
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$(srcroot)/include/gdb/sim-cr16.h
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# This selects the cr16 newlib/libgloss syscall definitions.
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@ -12914,7 +12914,7 @@ sim_link_links="${sim_link_links} targ-vals.def"
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wire_endian=""
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wire_endian="LITTLE_ENDIAN"
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default_endian=""
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# Check whether --enable-sim-endian was given.
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if test "${enable_sim_endian+set}" = set; then :
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@ -12958,8 +12958,8 @@ else
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fi
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fi
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wire_alignment="STRICT_ALIGNMENT"
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default_alignment="STRICT_ALIGNMENT"
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wire_alignment="NONSTRICT_ALIGNMENT"
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default_alignment=""
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# Check whether --enable-sim-alignment was given.
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if test "${enable_sim_alignment+set}" = set; then :
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@ -5,8 +5,8 @@ sinclude(../common/acinclude.m4)
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SIM_AC_COMMON
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SIM_AC_OPTION_ENDIAN
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SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT,STRICT_ALIGNMENT)
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SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
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SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
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SIM_AC_OPTION_HOSTENDIAN
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SIM_AC_OPTION_ENVIRONMENT
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SIM_AC_OPTION_INLINE
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@ -198,37 +198,6 @@ enum {
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} \
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while (0)
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/* cr16 memory: There are three separate cr16 memory regions IMEM,
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UMEM and DMEM. The IMEM and DMEM are further broken down into
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blocks (very like VM pages). */
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enum
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{
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IMAP_BLOCK_SIZE = 0x2000000,
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DMAP_BLOCK_SIZE = 0x4000000
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};
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/* Implement the three memory regions using sparse arrays. Allocate
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memory using ``segments''. A segment must be at least as large as
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a BLOCK - ensures that an access that doesn't cross a block
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boundary can't cross a segment boundary */
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enum
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{
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SEGMENT_SIZE = 0x2000000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
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IMEM_SEGMENTS = 8, /* 1MB */
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DMEM_SEGMENTS = 8, /* 1MB */
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UMEM_SEGMENTS = 128 /* 16MB */
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};
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struct cr16_memory
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{
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uint8 *insn[IMEM_SEGMENTS];
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uint8 *data[DMEM_SEGMENTS];
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uint8 *unif[UMEM_SEGMENTS];
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uint8 fault[16];
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};
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struct _state
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{
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creg_t regs[16]; /* general-purpose registers */
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@ -274,8 +243,6 @@ struct _state
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/* NOTE: everything below this line is not reset by
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sim_create_inferior() */
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struct cr16_memory mem;
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enum _ins_type ins_type;
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} State;
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@ -421,30 +388,19 @@ enum
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
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extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint32 offset);
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extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
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extern bfd_vma decode_pc (void);
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#define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
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#define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
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#define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
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#define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
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#define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
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#define RB(x) (*(dmem_addr (sd, cpu, x)))
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#define SB(addr,data) ( RB(addr) = (data & 0xff))
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#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
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#define ENDIAN_INLINE static __inline__
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#include "endian.c"
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#undef ENDIAN_INLINE
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#else
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extern uint32 get_longword (uint8 *);
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extern uint16 get_word (uint8 *);
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extern void write_word (uint8 *addr, uint16 data);
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extern void write_longword (uint8 *addr, uint32 data);
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#endif
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#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
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#define RW(x) get_word (dmem_addr (sd, cpu, x))
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#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
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#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
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#define READ_16(x) get_word(x)
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/* Yes, this is as whacked as it looks. The sim currently reads little endian
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for 16 bits, but then merge them like big endian to get 32 bits. */
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static inline uint32 get_longword (SIM_CPU *cpu, address_word addr)
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{
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return (RW (addr) << 16) | RW (addr + 2);
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}
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#define RLW(addr) get_longword (cpu, addr)
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#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
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@ -1,55 +0,0 @@
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/* Simulation code for the CR16 processor.
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Copyright (C) 2008-2015 Free Software Foundation, Inc.
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Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* If we're being compiled as a .c file, rather than being included in
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cr16_sim.h, then ENDIAN_INLINE won't be defined yet. */
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#ifndef ENDIAN_INLINE
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#define NO_ENDIAN_INLINE
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#include "sim-main.h"
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#define ENDIAN_INLINE
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#endif
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ENDIAN_INLINE uint16
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get_word (uint8 *x)
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{
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return *(uint16 *)x;
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}
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ENDIAN_INLINE uint32
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get_longword (uint8 *x)
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{
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return (((uint32) *(uint16 *)x) << 16) | ((uint32) *(uint16 *)(x+2));
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}
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ENDIAN_INLINE void
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write_word (uint8 *addr, uint16 data)
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{
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addr[1] = (data >> 8) & 0xff;
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addr[0] = data & 0xff;
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}
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ENDIAN_INLINE void
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write_longword (uint8 *addr, uint32 data)
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{
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*(uint16 *)(addr + 2) = (uint16)(data >> 16);
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*(uint16 *)(addr) = (uint16)data;
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}
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@ -42,7 +42,6 @@ uint32 sign_flag;
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static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size);
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static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
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static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
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#define MAX_HASH 16
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@ -335,7 +334,6 @@ do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
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struct simops *s= Simops;
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struct hash_entry *h;
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char func[12]="\0";
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uint8 *iaddr;
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#ifdef DEBUG
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if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
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(*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
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@ -346,11 +344,8 @@ do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
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if ((h == NULL) || (h->opcode == 0))
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return 0;
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if (h->size == 3)
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{
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iaddr = imem_addr (sd, cpu, (uint32)PC + 2);
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mcode = (mcode << 16) | get_longword( iaddr );
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}
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if (h->size == 3)
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mcode = (mcode << 16) | RW (PC + 4);
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/* Re-set OP list. */
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OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
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@ -370,389 +365,6 @@ do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
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return h->size;
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}
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static void
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sim_size (int power)
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{
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int i;
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for (i = 0; i < IMEM_SEGMENTS; i++)
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{
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if (State.mem.insn[i])
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free (State.mem.insn[i]);
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}
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for (i = 0; i < DMEM_SEGMENTS; i++)
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{
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if (State.mem.data[i])
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free (State.mem.data[i]);
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}
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for (i = 0; i < UMEM_SEGMENTS; i++)
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{
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if (State.mem.unif[i])
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free (State.mem.unif[i]);
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}
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/* Always allocate dmem segment 0. This contains the IMAP and DMAP
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registers. */
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State.mem.data[0] = calloc (1, SEGMENT_SIZE);
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}
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/* For tracing - leave info on last access around. */
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static char *last_segname = "invalid";
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static char *last_from = "invalid";
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static char *last_to = "invalid";
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enum
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{
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IMAP0_OFFSET = 0xff00,
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DMAP0_OFFSET = 0xff08,
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DMAP2_SHADDOW = 0xff04,
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DMAP2_OFFSET = 0xff0c
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};
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static unsigned long
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dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
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{
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uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA
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+ DMAP0_OFFSET + 2 * reg_nr);
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return READ_16 (raw);
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}
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static unsigned long
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imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
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{
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uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA
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+ IMAP0_OFFSET + 2 * reg_nr);
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return READ_16 (raw);
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}
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/* Given a virtual address in the DMAP address space, translate it
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into a physical address. */
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static unsigned long
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sim_cr16_translate_dmap_addr (SIM_DESC sd,
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SIM_CPU *cpu,
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unsigned long offset,
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int nr_bytes,
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unsigned long *phys,
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void *regcache,
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unsigned long (*dmap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr))
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{
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short map;
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int regno;
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last_from = "logical-data";
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if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS)
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{
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/* Logical address out side of data segments, not supported */
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return 0;
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}
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regno = (offset / DMAP_BLOCK_SIZE);
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offset = (offset % DMAP_BLOCK_SIZE);
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#if 1
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if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
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{
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/* Don't cross a BLOCK boundary */
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nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
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}
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map = dmap_register (sd, cpu, regcache, regno);
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if (regno == 3)
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{
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/* Always maps to data memory */
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int iospi = (offset / 0x1000) % 4;
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int iosp = (map >> (4 * (3 - iospi))) % 0x10;
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last_to = "io-space";
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*phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
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}
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else
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{
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int sp = ((map & 0x3000) >> 12);
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int segno = (map & 0x3ff);
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switch (sp)
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{
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case 0: /* 00: Unified memory */
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*phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
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last_to = "unified";
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break;
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case 1: /* 01: Instruction Memory */
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*phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
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last_to = "chip-insn";
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break;
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case 2: /* 10: Internal data memory */
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*phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
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last_to = "chip-data";
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break;
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case 3: /* 11: Reserved */
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return 0;
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}
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}
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#endif
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return nr_bytes;
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}
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/* Given a virtual address in the IMAP address space, translate it
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into a physical address. */
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static unsigned long
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sim_cr16_translate_imap_addr (SIM_DESC sd,
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SIM_CPU *cpu,
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unsigned long offset,
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int nr_bytes,
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unsigned long *phys,
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void *regcache,
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unsigned long (*imap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr))
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{
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short map;
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int regno;
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int sp;
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int segno;
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last_from = "logical-insn";
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if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS))
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{
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/* Logical address outside of IMAP segments, not supported */
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return 0;
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}
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regno = (offset / IMAP_BLOCK_SIZE);
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offset = (offset % IMAP_BLOCK_SIZE);
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if (offset + nr_bytes > IMAP_BLOCK_SIZE)
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{
|
||||
/* Don't cross a BLOCK boundary */
|
||||
nr_bytes = IMAP_BLOCK_SIZE - offset;
|
||||
}
|
||||
map = imap_register (sd, cpu, regcache, regno);
|
||||
sp = (map & 0x3000) >> 12;
|
||||
segno = (map & 0x007f);
|
||||
switch (sp)
|
||||
{
|
||||
case 0: /* 00: unified memory */
|
||||
*phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset;
|
||||
last_to = "unified";
|
||||
break;
|
||||
case 1: /* 01: instruction memory */
|
||||
*phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
|
||||
last_to = "chip-insn";
|
||||
break;
|
||||
case 2: /*10*/
|
||||
/* Reserved. */
|
||||
return 0;
|
||||
case 3: /* 11: for testing - instruction memory */
|
||||
offset = (offset % 0x800);
|
||||
*phys = SIM_CR16_MEMORY_INSN + offset;
|
||||
if (offset + nr_bytes > 0x800)
|
||||
/* don't cross VM boundary */
|
||||
nr_bytes = 0x800 - offset;
|
||||
last_to = "test-insn";
|
||||
break;
|
||||
}
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
sim_cr16_translate_addr (SIM_DESC sd,
|
||||
SIM_CPU *cpu,
|
||||
unsigned long memaddr,
|
||||
int nr_bytes,
|
||||
unsigned long *targ_addr,
|
||||
void *regcache,
|
||||
unsigned long (*dmap_register) (SIM_DESC,
|
||||
SIM_CPU *,
|
||||
void *regcache,
|
||||
int reg_nr),
|
||||
unsigned long (*imap_register) (SIM_DESC,
|
||||
SIM_CPU *,
|
||||
void *regcache,
|
||||
int reg_nr))
|
||||
{
|
||||
unsigned long phys;
|
||||
unsigned long seg;
|
||||
unsigned long off;
|
||||
|
||||
last_from = "unknown";
|
||||
last_to = "unknown";
|
||||
|
||||
seg = (memaddr >> 24);
|
||||
off = (memaddr & 0xffffffL);
|
||||
|
||||
switch (seg)
|
||||
{
|
||||
case 0x00: /* Physical unified memory */
|
||||
last_from = "phys-unified";
|
||||
last_to = "unified";
|
||||
phys = SIM_CR16_MEMORY_UNIFIED + off;
|
||||
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
|
||||
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
|
||||
break;
|
||||
|
||||
case 0x01: /* Physical instruction memory */
|
||||
last_from = "phys-insn";
|
||||
last_to = "chip-insn";
|
||||
phys = SIM_CR16_MEMORY_INSN + off;
|
||||
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
|
||||
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
|
||||
break;
|
||||
|
||||
case 0x02: /* Physical data memory segment */
|
||||
last_from = "phys-data";
|
||||
last_to = "chip-data";
|
||||
phys = SIM_CR16_MEMORY_DATA + off;
|
||||
if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
|
||||
nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
|
||||
break;
|
||||
|
||||
case 0x10: /* in logical data address segment */
|
||||
nr_bytes = sim_cr16_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys,
|
||||
regcache, dmap_register);
|
||||
break;
|
||||
|
||||
case 0x11: /* in logical instruction address segment */
|
||||
nr_bytes = sim_cr16_translate_imap_addr (sd, cpu, off, nr_bytes, &phys,
|
||||
regcache, imap_register);
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
*targ_addr = phys;
|
||||
return nr_bytes;
|
||||
}
|
||||
|
||||
/* Return a pointer into the raw buffer designated by phys_addr. It
|
||||
is assumed that the client has already ensured that the access
|
||||
isn't going to cross a segment boundary. */
|
||||
|
||||
uint8 *
|
||||
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
|
||||
{
|
||||
uint8 **memory;
|
||||
uint8 *raw;
|
||||
unsigned offset;
|
||||
int segment = ((phys_addr >> 24) & 0xff);
|
||||
|
||||
switch (segment)
|
||||
{
|
||||
|
||||
case 0x00: /* Unified memory */
|
||||
{
|
||||
memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
|
||||
last_segname = "umem";
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x01: /* On-chip insn memory */
|
||||
{
|
||||
memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
|
||||
last_segname = "imem";
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x02: /* On-chip data memory */
|
||||
{
|
||||
if ((phys_addr & 0xff00) == 0xff00)
|
||||
{
|
||||
phys_addr = (phys_addr & 0xffff);
|
||||
if (phys_addr == DMAP2_SHADDOW)
|
||||
{
|
||||
phys_addr = DMAP2_OFFSET;
|
||||
last_segname = "dmap";
|
||||
}
|
||||
else
|
||||
last_segname = "reg";
|
||||
}
|
||||
else
|
||||
last_segname = "dmem";
|
||||
memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
/* OOPS! */
|
||||
last_segname = "scrap";
|
||||
return State.mem.fault;
|
||||
}
|
||||
|
||||
if (*memory == NULL)
|
||||
{
|
||||
*memory = calloc (1, SEGMENT_SIZE);
|
||||
if (*memory == NULL)
|
||||
{
|
||||
(*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
|
||||
return State.mem.fault;
|
||||
}
|
||||
}
|
||||
|
||||
offset = (phys_addr % SEGMENT_SIZE);
|
||||
raw = *memory + offset;
|
||||
return raw;
|
||||
}
|
||||
|
||||
/* Transfer data to/from simulated memory. Since a bug in either the
|
||||
simulated program or in gdb or the simulator itself may cause a
|
||||
bogus address to be passed in, we need to do some sanity checking
|
||||
on addresses to make sure they are within bounds. When an address
|
||||
fails the bounds check, treat it as a zero length read/write rather
|
||||
than aborting the entire run. */
|
||||
|
||||
static int
|
||||
xfer_mem (SIM_DESC sd, SIM_ADDR virt,
|
||||
unsigned char *buffer,
|
||||
int size,
|
||||
int write_p)
|
||||
{
|
||||
host_callback *cr16_callback = STATE_CALLBACK (sd);
|
||||
uint8 *memory;
|
||||
unsigned long phys;
|
||||
int phys_size;
|
||||
phys_size = sim_cr16_translate_addr (sd, NULL, virt, size, &phys, NULL,
|
||||
dmap_register, imap_register);
|
||||
if (phys_size == 0)
|
||||
return 0;
|
||||
|
||||
memory = map_memory (sd, NULL, phys);
|
||||
|
||||
#ifdef DEBUG
|
||||
if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
|
||||
{
|
||||
(*cr16_callback->printf_filtered)
|
||||
(cr16_callback,
|
||||
"sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
|
||||
(write_p ? "write" : "read"),
|
||||
phys_size, virt, last_from,
|
||||
phys, last_to,
|
||||
(long) memory, last_segname);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (write_p)
|
||||
{
|
||||
memcpy (memory, buffer, phys_size);
|
||||
}
|
||||
else
|
||||
{
|
||||
memcpy (buffer, memory, phys_size);
|
||||
}
|
||||
|
||||
return phys_size;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
|
||||
{
|
||||
/* FIXME: this should be performing a virtual transfer */
|
||||
return xfer_mem (sd, addr, buffer, size, 1);
|
||||
}
|
||||
|
||||
int
|
||||
sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
|
||||
{
|
||||
/* FIXME: this should be performing a virtual transfer */
|
||||
return xfer_mem (sd, addr, buffer, size, 0);
|
||||
}
|
||||
|
||||
static sim_cia
|
||||
cr16_pc_get (sim_cpu *cpu)
|
||||
{
|
||||
|
|
@ -848,6 +460,14 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd,
|
|||
CPU_PC_STORE (cpu) = cr16_pc_set;
|
||||
}
|
||||
|
||||
/* The CR16 has an interrupt controller at 0xFC00, but we don't currently
|
||||
handle that. Revisit if anyone ever implements operating mode. */
|
||||
/* cr16 memory: There are three separate cr16 memory regions IMEM,
|
||||
UMEM and DMEM. The IMEM and DMEM are further broken down into
|
||||
blocks (very like VM pages). This might not match the hardware,
|
||||
but it matches what the toolchain currently expects. Ugh. */
|
||||
sim_do_commandf (sd, "memory-size %#x", 20 * 1024 * 1024);
|
||||
|
||||
cr16_callback = cb;
|
||||
|
||||
/* put all the opcodes in the hash table. */
|
||||
|
|
@ -956,72 +576,9 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd,
|
|||
}
|
||||
}
|
||||
|
||||
/* reset the processor state */
|
||||
if (!State.mem.data[0])
|
||||
sim_size (1);
|
||||
|
||||
return sd;
|
||||
}
|
||||
|
||||
uint8 *
|
||||
dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
|
||||
{
|
||||
unsigned long phys;
|
||||
uint8 *mem;
|
||||
int phys_size;
|
||||
|
||||
/* Note: DMEM address range is 0..0x10000. Calling code can compute
|
||||
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
|
||||
is uint16 this is modulo'ed onto 0x0e5d. */
|
||||
|
||||
phys_size = sim_cr16_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
|
||||
dmap_register);
|
||||
if (phys_size == 0)
|
||||
{
|
||||
mem = State.mem.fault;
|
||||
}
|
||||
else
|
||||
mem = map_memory (sd, cpu, phys);
|
||||
#ifdef DEBUG
|
||||
if ((cr16_debug & DEBUG_MEMORY))
|
||||
{
|
||||
(*cr16_callback->printf_filtered)
|
||||
(cr16_callback,
|
||||
"mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
|
||||
offset, last_from,
|
||||
phys, phys_size, last_to,
|
||||
(long) mem, last_segname);
|
||||
}
|
||||
#endif
|
||||
return mem;
|
||||
}
|
||||
|
||||
uint8 *
|
||||
imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
|
||||
{
|
||||
unsigned long phys;
|
||||
uint8 *mem;
|
||||
int phys_size = sim_cr16_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
|
||||
imap_register);
|
||||
if (phys_size == 0)
|
||||
{
|
||||
return State.mem.fault;
|
||||
}
|
||||
mem = map_memory (sd, cpu, phys);
|
||||
#ifdef DEBUG
|
||||
if ((cr16_debug & DEBUG_MEMORY))
|
||||
{
|
||||
(*cr16_callback->printf_filtered)
|
||||
(cr16_callback,
|
||||
"mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
|
||||
offset, last_from,
|
||||
phys, phys_size, last_to,
|
||||
(long) mem, last_segname);
|
||||
}
|
||||
#endif
|
||||
return mem;
|
||||
}
|
||||
|
||||
static int stop_simulator = 0;
|
||||
|
||||
int
|
||||
|
|
@ -1038,8 +595,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
|
|||
{
|
||||
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
||||
uint32 curr_ins_size = 0;
|
||||
uint64 mcode = 0;
|
||||
uint8 *iaddr;
|
||||
uint64 mcode;
|
||||
|
||||
#ifdef DEBUG
|
||||
// (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC);
|
||||
|
|
@ -1076,19 +632,8 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
|
|||
|
||||
do
|
||||
{
|
||||
iaddr = imem_addr (sd, cpu, (uint32)PC);
|
||||
if (iaddr == State.mem.fault)
|
||||
{
|
||||
#ifdef SIGBUS
|
||||
State.exception = SIGBUS;
|
||||
#else
|
||||
State.exception = SIGSEGV;
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
mcode = get_longword( iaddr );
|
||||
|
||||
mcode = RLW (PC);
|
||||
|
||||
State.pc_changed = 0;
|
||||
|
||||
curr_ins_size = do_run (sd, cpu, mcode);
|
||||
|
|
@ -1134,7 +679,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
|
|||
bfd_vma start_address;
|
||||
|
||||
/* reset all state information */
|
||||
memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs);
|
||||
memset (&State, 0, sizeof (State));
|
||||
|
||||
/* There was a hack here to copy the values of argc and argv into r0
|
||||
and r1. The values were also saved into some high memory that
|
||||
|
|
|
|||
|
|
@ -5143,7 +5143,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
|
|||
|
||||
/* Turn a pointer in a register into a pointer into real memory. */
|
||||
|
||||
#define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
|
||||
#define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
|
||||
|
||||
switch (FUNC)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue