[PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operand. (parse_operands): Handle new operand. (mve_encode_qqr): Change to support new instructions. (enum vfp_or_neon_is_neon_bits): Moved. (vfp_or_neon_is_neon): Moved. (check_simd_pred_availability): Moved. (do_neon_dyadic_i_su): Changed to support MVE variants. (neon_dyadic_misc): Changed mve_encode_qqr call. (do_mve_vbrsr): Likewise. (do_mve_vhcadd): New encoding function. (insns): Change existing to accept MVE variants and add new. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test. * testsuite/gas/arm/mve-vhcadd-bad.d: New test. * testsuite/gas/arm/mve-vhcadd-bad.l: New test. * testsuite/gas/arm/mve-vhcadd-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
d58196e061
commit
7df5412033
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@ -1,3 +1,23 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): New operand.
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(parse_operands): Handle new operand.
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(mve_encode_qqr): Change to support new instructions.
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(enum vfp_or_neon_is_neon_bits): Moved.
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(vfp_or_neon_is_neon): Moved.
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(check_simd_pred_availability): Moved.
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(do_neon_dyadic_i_su): Changed to support MVE variants.
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(neon_dyadic_misc): Changed mve_encode_qqr call.
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(do_mve_vbrsr): Likewise.
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(do_mve_vhcadd): New encoding function.
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(insns): Change existing to accept MVE variants and add new.
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* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.
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* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.
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* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.
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* testsuite/gas/arm/mve-vhcadd-bad.d: New test.
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* testsuite/gas/arm/mve-vhcadd-bad.l: New test.
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* testsuite/gas/arm/mve-vhcadd-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.
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@ -6902,6 +6902,7 @@ enum operand_parse_code
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OP_RNSD, /* Neon single or double precision register */
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OP_RNDQ, /* Neon double or quad precision register */
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OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
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OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
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OP_RNSDQ, /* Neon single, double or quad precision register */
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OP_RNSC, /* Neon scalar D[X] */
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OP_RVC, /* VFP control register */
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@ -7242,6 +7243,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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try_nq:
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case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
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case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
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case OP_RNDQMQR:
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po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
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break;
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try_rndqmq:
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case OP_oRNDQMQ:
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case OP_RNDQMQ:
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po_reg_or_goto (REG_TYPE_MQ, try_rndq);
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@ -15820,7 +15825,7 @@ neon_dp_fixup (struct arm_it* insn)
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}
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static void
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mve_encode_qqr (int size, int fp)
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mve_encode_qqr (int size, int U, int fp)
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{
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if (inst.operands[2].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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@ -15847,6 +15852,16 @@ mve_encode_qqr (int size, int fp)
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/* vsub. */
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else if (((unsigned)inst.instruction) == 0x1000800)
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inst.instruction = 0xee011f40;
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/* vhadd. */
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else if (((unsigned)inst.instruction) == 0)
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inst.instruction = 0xee000f40;
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/* vhsub. */
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else if (((unsigned)inst.instruction) == 0x200)
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inst.instruction = 0xee001f40;
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/* Set U-bit. */
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inst.instruction |= U << 28;
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/* Setting bits for size. */
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inst.instruction |= neon_logbits (size) << 20;
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}
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@ -15945,15 +15960,112 @@ neon_two_same (int qbit, int ubit, int size)
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neon_dp_fixup (&inst);
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}
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enum vfp_or_neon_is_neon_bits
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{
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NEON_CHECK_CC = 1,
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NEON_CHECK_ARCH = 2,
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NEON_CHECK_ARCH8 = 4
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};
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/* Call this function if an instruction which may have belonged to the VFP or
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Neon instruction sets, but turned out to be a Neon instruction (due to the
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operand types involved, etc.). We have to check and/or fix-up a couple of
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things:
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- Make sure the user hasn't attempted to make a Neon instruction
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conditional.
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- Alter the value in the condition code field if necessary.
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- Make sure that the arch supports Neon instructions.
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Which of these operations take place depends on bits from enum
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vfp_or_neon_is_neon_bits.
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WARNING: This function has side effects! If NEON_CHECK_CC is used and the
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current instruction's condition is COND_ALWAYS, the condition field is
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changed to inst.uncond_value. This is necessary because instructions shared
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between VFP and Neon may be conditional for the VFP variants only, and the
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unconditional Neon version must have, e.g., 0xF in the condition field. */
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static int
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vfp_or_neon_is_neon (unsigned check)
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{
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/* Conditions are always legal in Thumb mode (IT blocks). */
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if (!thumb_mode && (check & NEON_CHECK_CC))
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{
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if (inst.cond != COND_ALWAYS)
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{
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first_error (_(BAD_COND));
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return FAIL;
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}
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if (inst.uncond_value != -1)
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inst.instruction |= inst.uncond_value << 28;
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}
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if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
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|| ((check & NEON_CHECK_ARCH8)
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&& !mark_feature_used (&fpu_neon_ext_armv8)))
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{
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first_error (_(BAD_FPU));
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return FAIL;
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}
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return SUCCESS;
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}
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static int
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check_simd_pred_availability (int fp, unsigned check)
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{
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if (inst.cond > COND_ALWAYS)
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{
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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inst.error = BAD_FPU;
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return 1;
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}
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inst.pred_insn_type = INSIDE_VPT_INSN;
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}
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else if (inst.cond < COND_ALWAYS)
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{
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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else if (vfp_or_neon_is_neon (check) == FAIL)
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return 2;
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}
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else
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{
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
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&& vfp_or_neon_is_neon (check) == FAIL)
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return 3;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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}
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return 0;
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}
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/* Neon instruction encoders, in approximate order of appearance. */
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static void
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do_neon_dyadic_i_su (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_SU_32 | N_KEY);
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neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
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else
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rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
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if (rs != NS_QQR)
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neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
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else
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mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
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}
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static void
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@ -16120,90 +16232,6 @@ neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
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return FAIL;
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}
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enum vfp_or_neon_is_neon_bits
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{
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NEON_CHECK_CC = 1,
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NEON_CHECK_ARCH = 2,
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NEON_CHECK_ARCH8 = 4
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};
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/* Call this function if an instruction which may have belonged to the VFP or
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Neon instruction sets, but turned out to be a Neon instruction (due to the
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operand types involved, etc.). We have to check and/or fix-up a couple of
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things:
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- Make sure the user hasn't attempted to make a Neon instruction
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conditional.
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- Alter the value in the condition code field if necessary.
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- Make sure that the arch supports Neon instructions.
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Which of these operations take place depends on bits from enum
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vfp_or_neon_is_neon_bits.
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WARNING: This function has side effects! If NEON_CHECK_CC is used and the
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current instruction's condition is COND_ALWAYS, the condition field is
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changed to inst.uncond_value. This is necessary because instructions shared
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between VFP and Neon may be conditional for the VFP variants only, and the
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unconditional Neon version must have, e.g., 0xF in the condition field. */
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static int
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vfp_or_neon_is_neon (unsigned check)
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{
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/* Conditions are always legal in Thumb mode (IT blocks). */
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if (!thumb_mode && (check & NEON_CHECK_CC))
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{
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if (inst.cond != COND_ALWAYS)
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{
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first_error (_(BAD_COND));
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return FAIL;
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}
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if (inst.uncond_value != -1)
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inst.instruction |= inst.uncond_value << 28;
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}
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if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
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|| ((check & NEON_CHECK_ARCH8)
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&& !mark_feature_used (&fpu_neon_ext_armv8)))
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{
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first_error (_(BAD_FPU));
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return FAIL;
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}
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return SUCCESS;
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}
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static int
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check_simd_pred_availability (int fp, unsigned check)
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{
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if (inst.cond > COND_ALWAYS)
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{
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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inst.error = BAD_FPU;
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return 1;
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}
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inst.pred_insn_type = INSIDE_VPT_INSN;
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}
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else if (inst.cond < COND_ALWAYS)
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{
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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else if (vfp_or_neon_is_neon (check) == FAIL)
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return 2;
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}
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else
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{
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
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&& vfp_or_neon_is_neon (check) == FAIL)
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return 3;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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}
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return 0;
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}
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static void
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do_neon_logic (void)
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{
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@ -16332,7 +16360,7 @@ neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
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{
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NEON_ENCODE (FLOAT, inst);
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if (rs == NS_QQR)
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mve_encode_qqr (et.size, 1);
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mve_encode_qqr (et.size, 0, 1);
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else
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neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
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}
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@ -16340,7 +16368,7 @@ neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
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{
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NEON_ENCODE (INTEGER, inst);
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if (rs == NS_QQR)
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mve_encode_qqr (et.size, 0);
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mve_encode_qqr (et.size, 0, 0);
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else
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neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
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}
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@ -16991,6 +17019,30 @@ do_mve_vaddv (void)
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mve_encode_rq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vhcadd (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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unsigned rot = inst.relocs[0].exp.X_add_number;
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constraint (rot != 90 && rot != 270, _("immediate out of range"));
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if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
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as_tsktsk (_("Warning: 32-bit element size and same first and third "
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"operand makes instruction UNPREDICTABLE"));
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mve_encode_qqq (0, et.size);
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inst.instruction |= (rot == 270) << 12;
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inst.is_neon = 1;
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}
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static void
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do_mve_vadc (void)
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{
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@ -17021,7 +17073,7 @@ do_mve_vbrsr (void)
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_qqr (et.size, 0);
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mve_encode_qqr (et.size, 0, 0);
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}
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static void
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@ -23585,11 +23637,8 @@ static const struct asm_opcode insns[] =
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/* integer ops, valid types S8 S16 S32 U8 U16 U32. */
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NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
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NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
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NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
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NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
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NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
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NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
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NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
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NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
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/* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
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NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
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@ -24271,6 +24320,7 @@ static const struct asm_opcode insns[] =
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ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
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/* MVE and MVE FP only. */
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mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
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mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
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mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
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mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
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@ -24383,6 +24433,9 @@ static const struct asm_opcode insns[] =
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MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
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MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
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mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
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MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
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MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
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MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VHADD, VHSUB and VRHADD instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vhadd-vhsub-vrhadd-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,71 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vhadd.i8 q0,q1,q2'
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||||
[^:]*:11: Error: bad type in SIMD instruction -- `vhadd.s64 q0,q1,q2'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vhadd.i8 q0,q1,r2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vhadd.s64 q0,q1,r2'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vhsub.i16 q0,q1,q2'
|
||||
[^:]*:15: Error: bad type in SIMD instruction -- `vhsub.u64 q0,q1,q2'
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vhsub.i16 q0,q1,r2'
|
||||
[^:]*:17: Error: bad type in SIMD instruction -- `vhsub.u64 q0,q1,r2'
|
||||
[^:]*:18: Error: bad type in SIMD instruction -- `vrhadd.i32 q0,q1,q2'
|
||||
[^:]*:19: Error: bad type in SIMD instruction -- `vrhadd.s64 q0,q1,q2'
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
[^:]*:22: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:23: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
[^:]*:24: Error: garbage following instruction -- `vrhadd.s8 q0,q1,r2'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:31: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
|
||||
[^:]*:32: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
|
||||
[^:]*:34: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
|
||||
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vhaddt.s8 q0,q1,r2'
|
||||
[^:]*:37: Error: instruction missing MVE vector predication code -- `vhadd.s8 q0,q1,r2'
|
||||
[^:]*:39: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:40: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:42: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vhaddt.s8 q0,q1,q2'
|
||||
[^:]*:45: Error: instruction missing MVE vector predication code -- `vhadd.s8 q0,q1,q2'
|
||||
[^:]*:47: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
|
||||
[^:]*:48: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
|
||||
[^:]*:50: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
|
||||
[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vhsubt.s8 q0,q1,r2'
|
||||
[^:]*:53: Error: instruction missing MVE vector predication code -- `vhsub.s8 q0,q1,r2'
|
||||
[^:]*:55: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
|
||||
[^:]*:56: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
|
||||
[^:]*:58: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
|
||||
[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vhsubt.s8 q0,q1,q2'
|
||||
[^:]*:61: Error: instruction missing MVE vector predication code -- `vhsub.s8 q0,q1,q2'
|
||||
[^:]*:63: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:64: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:66: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
|
||||
[^:]*:67: Error: vector predicated instruction should be in VPT/VPST block -- `vrhaddt.s8 q0,q1,q2'
|
||||
[^:]*:69: Error: instruction missing MVE vector predication code -- `vrhadd.s8 q0,q1,q2'
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
.macro cond, op, lastreg
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s8 q0, q1, \lastreg
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vhadd.i8 q0, q1, q2
|
||||
vhadd.s64 q0, q1, q2
|
||||
vhadd.i8 q0, q1, r2
|
||||
vhadd.s64 q0, q1, r2
|
||||
vhsub.i16 q0, q1, q2
|
||||
vhsub.u64 q0, q1, q2
|
||||
vhsub.i16 q0, q1, r2
|
||||
vhsub.u64 q0, q1, r2
|
||||
vrhadd.i32 q0, q1, q2
|
||||
vrhadd.s64 q0, q1, q2
|
||||
vhadd.s8 q0, q1, sp
|
||||
vhadd.s8 q0, q1, pc
|
||||
vhsub.s8 q0, q1, sp
|
||||
vhsub.s8 q0, q1, pc
|
||||
vrhadd.s8 q0, q1, r2
|
||||
cond vhadd, r2
|
||||
cond vhadd, q2
|
||||
cond vhsub, r2
|
||||
cond vhsub, q2
|
||||
cond vrhadd, q2
|
||||
it eq
|
||||
vhaddeq.s8 q0, q1, r2
|
||||
vhaddeq.s8 q0, q1, r2
|
||||
vpst
|
||||
vhaddeq.s8 q0, q1, r2
|
||||
vhaddt.s8 q0, q1, r2
|
||||
vpst
|
||||
vhadd.s8 q0, q1, r2
|
||||
it eq
|
||||
vhaddeq.s8 q0, q1, q2
|
||||
vhaddeq.s8 q0, q1, q2
|
||||
vpst
|
||||
vhaddeq.s8 q0, q1, q2
|
||||
vhaddt.s8 q0, q1, q2
|
||||
vpst
|
||||
vhadd.s8 q0, q1, q2
|
||||
it eq
|
||||
vhsubeq.s8 q0, q1, r2
|
||||
vhsubeq.s8 q0, q1, r2
|
||||
vpst
|
||||
vhsubeq.s8 q0, q1, r2
|
||||
vhsubt.s8 q0, q1, r2
|
||||
vpst
|
||||
vhsub.s8 q0, q1, r2
|
||||
it eq
|
||||
vhsubeq.s8 q0, q1, q2
|
||||
vhsubeq.s8 q0, q1, q2
|
||||
vpst
|
||||
vhsubeq.s8 q0, q1, q2
|
||||
vhsubt.s8 q0, q1, q2
|
||||
vpst
|
||||
vhsub.s8 q0, q1, q2
|
||||
it eq
|
||||
vrhaddeq.s8 q0, q1, q2
|
||||
vrhaddeq.s8 q0, q1, q2
|
||||
vpst
|
||||
vrhaddeq.s8 q0, q1, q2
|
||||
vrhaddt.s8 q0, q1, q2
|
||||
vpst
|
||||
vrhadd.s8 q0, q1, q2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VHCADD instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vhcadd-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vhcadd.u8 q0,q1,q2,#90'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vhcadd.i8 q0,q1,q2,#90'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vhcadd.s64 q0,q1,q2,#90'
|
||||
[^:]*:13: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#0'
|
||||
[^:]*:14: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#180'
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
|
||||
[^:]*:18: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
|
||||
[^:]*:20: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vhcaddt.s8 q0,q1,q2,#90'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vhcadd.s8 q0,q1,q2,#90'
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
.macro cond
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vhcadd.s8 q0, q1, q2, #90
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vhcadd.u8 q0, q1, q2, #90
|
||||
vhcadd.i8 q0, q1, q2, #90
|
||||
vhcadd.s64 q0, q1, q2, #90
|
||||
vhcadd.s8 q0, q1, q2, #0
|
||||
vhcadd.s8 q0, q1, q2, #180
|
||||
cond
|
||||
it eq
|
||||
vhcaddeq.s8 q0, q1, q2, #90
|
||||
vhcaddeq.s8 q0, q1, q2, #90
|
||||
vpst
|
||||
vhcaddeq.s8 q0, q1, q2, #90
|
||||
vhcaddt.s8 q0, q1, q2, #90
|
||||
vpst
|
||||
vhcadd.s8 q0, q1, q2, #90
|
||||
Loading…
Reference in New Issue