[PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_fmac): Change to support MVE variants. (insns): Change to accept MVE variants. * testsuite/gas/arm/mve-vfma-vfms-bad.d: New test. * testsuite/gas/arm/mve-vfma-vfms-bad.l: New test. * testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
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Andre Vieira
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@ -1,3 +1,11 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.
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(insns): Change to accept MVE variants.
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* testsuite/gas/arm/mve-vfma-vfms-bad.d: New test.
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* testsuite/gas/arm/mve-vfma-vfms-bad.l: New test.
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* testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
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@ -16882,12 +16882,42 @@ do_neon_mac_maybe_scalar (void)
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static void
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do_neon_fmac (void)
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{
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if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
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if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
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&& try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
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return;
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
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if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
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return;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
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{
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enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
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N_EQK);
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if (rs == NS_QQR)
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{
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if (inst.operands[2].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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else if (inst.operands[2].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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inst.instruction = 0xee310e40;
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inst.instruction |= (et.size == 16) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 6;
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inst.instruction |= inst.operands[2].reg;
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inst.is_neon = 1;
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return;
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}
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}
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else
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{
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constraint (!inst.operands[2].isvec, BAD_FPU);
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}
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neon_dyadic_misc (NT_untyped, N_IF_32, 0);
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}
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@ -23819,11 +23849,12 @@ static const struct asm_opcode insns[] =
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#define ARM_VARIANT & fpu_vfp_ext_fma
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & fpu_vfp_ext_fma
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/* Mnemonics shared by Neon and VFP. These are included in the
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/* Mnemonics shared by Neon, VFP and MVE. These are included in the
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VFP FMA variant; NEON and VFP FMA always includes the NEON
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FMA instructions. */
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nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
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nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
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mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
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mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
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/* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
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the v form should always be used. */
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cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
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5
gas/testsuite/gas/arm/mve-vfma-vfms-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vfma-vfms-bad.d
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@ -0,0 +1,5 @@
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#name: bad MVE FP VFMA and VFMS instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vfma-vfms-bad.l
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.*: +file format .*arm.*
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35
gas/testsuite/gas/arm/mve-vfma-vfms-bad.l
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35
gas/testsuite/gas/arm/mve-vfma-vfms-bad.l
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@ -0,0 +1,35 @@
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[^:]*: Assembler messages:
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[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:25: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:26: Error: bad type in SIMD instruction -- `vfma.f64 q0,q1,q2'
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[^:]*:27: Error: bad type in SIMD instruction -- `vfma.32 q0,q1,q2'
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[^:]*:28: Error: bad type in SIMD instruction -- `vfms.f64 q0,q1,q2'
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[^:]*:29: Error: bad type in SIMD instruction -- `vfms.32 q0,q1,q2'
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:32: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:33: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:35: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
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[^:]*:36: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
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[^:]*:38: Error: syntax error -- `vfmaeq.f16 q0,q1,q2'
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[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vfmat.f16 q0,q1,q2'
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[^:]*:41: Error: instruction missing MVE vector predication code -- `vfma.f16 q0,q1,q2'
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[^:]*:43: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
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[^:]*:44: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
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[^:]*:46: Error: syntax error -- `vfmseq.f16 q0,q1,q2'
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[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vfmst.f16 q0,q1,q2'
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[^:]*:49: Error: instruction missing MVE vector predication code -- `vfms.f16 q0,q1,q2'
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49
gas/testsuite/gas/arm/mve-vfma-vfms-bad.s
Normal file
49
gas/testsuite/gas/arm/mve-vfma-vfms-bad.s
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@ -0,0 +1,49 @@
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.macro cond1
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vfma.f32 q0, q1, q2
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.endr
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.endm
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.macro cond2
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vfma.f32 q0, q1, r2
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.endr
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.endm
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.macro cond3
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vfms.f32 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vfma.f32 q0, q1, sp
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vfma.f32 q0, q1, pc
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vfma.f64 q0, q1, q2
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vfma.32 q0, q1, q2
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vfms.f64 q0, q1, q2
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vfms.32 q0, q1, q2
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vfma.f64 d0, d1, d2
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cond1
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cond2
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cond3
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it eq
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vfmaeq.f16 q0, q1, q2
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vfmaeq.f16 q0, q1, q2
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vpst
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vfmaeq.f16 q0, q1, q2
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vfmat.f16 q0, q1, q2
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vpst
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vfma.f16 q0, q1, q2
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it eq
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vfmseq.f16 q0, q1, q2
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vfmseq.f16 q0, q1, q2
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vpst
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vfmseq.f16 q0, q1, q2
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vfmst.f16 q0, q1, q2
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vpst
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vfms.f16 q0, q1, q2
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