MIPS: Add new Imagination interAptiv MR2 GAS and LD tests
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly,
disassembly and ELF object file flags.
Add LD tests to verify Imagination interAptiv MR2 ELF object file
link-time compatibility and flag merging/propagation. Use the framework
enhancement added with commit 7575e6a752 ("MIPS/LD/testsuite:
mips-elf-flags: Add MIPS ABI Flags handling").
gas/
* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
* testsuite/gas/mips/save-err.d: New test.
* testsuite/gas/mips/save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
* testsuite/gas/mips/mips1@save-sub.d: New test.
* testsuite/gas/mips/mips2@save-sub.d: New test.
* testsuite/gas/mips/mips3@save-sub.d: New test.
* testsuite/gas/mips/mips4@save-sub.d: New test.
* testsuite/gas/mips/mips5@save-sub.d: New test.
* testsuite/gas/mips/mips32@save-sub.d: New test.
* testsuite/gas/mips/mips64@save-sub.d: New test.
* testsuite/gas/mips/mips16@save-sub.d: New test.
* testsuite/gas/mips/mips16e@save-sub.d: New test.
* testsuite/gas/mips/r3000@save-sub.d: New test.
* testsuite/gas/mips/r3900@save-sub.d: New test.
* testsuite/gas/mips/r4000@save-sub.d: New test.
* testsuite/gas/mips/vr5400@save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
* testsuite/gas/mips/sb1@save-sub.d: New test.
* testsuite/gas/mips/octeon2@save-sub.d: New test.
* testsuite/gas/mips/octeon3@save-sub.d: New test.
* testsuite/gas/mips/xlr@save-sub.d: New test.
* testsuite/gas/mips/r5900@save-sub.d: New test.
* testsuite/gas/mips/mips16e2-copy.d: New test.
* testsuite/gas/mips/mips16e2-copy-err.d: New test.
* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
option. Adjust for trailing padding change.
* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
* testsuite/gas/mips/save-sub.s: New test source.
* testsuite/gas/mips/mips16e2-copy.s: New test source.
* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
* testsuite/gas/mips/save.s: Update description, change trailing
padding and remove trailing white space.
* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
tests across the regular MIPS interAptiv MR2 architecture. Run
the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2
tests.
This commit is contained in:
Maciej W. Rozycki
parent
c7d289d129
commit
819e1f8697
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@ -1,3 +1,42 @@
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2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
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* testsuite/gas/mips/save-err.d: New test.
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* testsuite/gas/mips/save-sub.d: New test.
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* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
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* testsuite/gas/mips/mips1@save-sub.d: New test.
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* testsuite/gas/mips/mips2@save-sub.d: New test.
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* testsuite/gas/mips/mips3@save-sub.d: New test.
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* testsuite/gas/mips/mips4@save-sub.d: New test.
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* testsuite/gas/mips/mips5@save-sub.d: New test.
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* testsuite/gas/mips/mips32@save-sub.d: New test.
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* testsuite/gas/mips/mips64@save-sub.d: New test.
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* testsuite/gas/mips/mips16@save-sub.d: New test.
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* testsuite/gas/mips/mips16e@save-sub.d: New test.
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* testsuite/gas/mips/r3000@save-sub.d: New test.
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* testsuite/gas/mips/r3900@save-sub.d: New test.
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* testsuite/gas/mips/r4000@save-sub.d: New test.
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* testsuite/gas/mips/vr5400@save-sub.d: New test.
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* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
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* testsuite/gas/mips/sb1@save-sub.d: New test.
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* testsuite/gas/mips/octeon2@save-sub.d: New test.
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* testsuite/gas/mips/octeon3@save-sub.d: New test.
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* testsuite/gas/mips/xlr@save-sub.d: New test.
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* testsuite/gas/mips/r5900@save-sub.d: New test.
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* testsuite/gas/mips/mips16e2-copy.d: New test.
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* testsuite/gas/mips/mips16e2-copy-err.d: New test.
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* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
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option. Adjust for trailing padding change.
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* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
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* testsuite/gas/mips/save-sub.s: New test source.
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* testsuite/gas/mips/mips16e2-copy.s: New test source.
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* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
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* testsuite/gas/mips/save.s: Update description, change trailing
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padding and remove trailing white space.
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* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
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tests across the regular MIPS interAptiv MR2 architecture. Run
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the new tests.
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2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
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@ -0,0 +1,24 @@
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#readelf: -Ah
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#name: ELF interAptiv MR2 markings
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#as: -32 -march=interaptiv-mr2
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#source: empty.s
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ELF Header:
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#...
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Flags: +0x..93...., .*interaptiv-mr2.*
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#...
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MIPS ABI Flags Version: 0
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ISA: MIPS32r3
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GPR size: 32
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CPR1 size: 32
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CPR2 size: 0
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FP ABI: .*
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ISA Extension: Imagination interAptiv MR2
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ASEs:
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DSP ASE
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Enhanced VA Scheme
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MT ASE
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FLAGS 1: .*
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FLAGS 2: .*
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@ -0,0 +1,44 @@
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#objdump: -dr
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#as: -32 -I$srcdir/$subdir
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#name: SAVE/RESTORE instruction subset disassembly
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#source: save-sub.s
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.*: +file format .*mips.*
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Disassembly of section .text:
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00000000 <func>:
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0:[ ]+7000205f[ ]+save[ ]+8
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4:[ ]+7000309f[ ]+save[ ]+16,ra
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8:[ ]+700028df[ ]+save[ ]+24,s0
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c:[ ]+7000251f[ ]+save[ ]+32,s1
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10:[ ]+70002d5f[ ]+save[ ]+40,s0-s1
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14:[ ]+7000399f[ ]+save[ ]+48,ra,s0
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18:[ ]+700035df[ ]+save[ ]+56,ra,s1
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1c:[ ]+70003e1f[ ]+save[ ]+64,ra,s0-s1
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20:[ ]+70003e5f[ ]+save[ ]+72,ra,s0-s1
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24:[ ]+70003e9f[ ]+save[ ]+80,ra,s0-s1
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28:[ ]+70003edf[ ]+save[ ]+88,ra,s0-s1
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2c:[ ]+70083c1f[ ]+save[ ]+128,ra,s0-s1
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30:[ ]+7008205f[ ]+save[ ]+136
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34:[ ]+7008309f[ ]+save[ ]+144,ra
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38:[ ]+70082cdf[ ]+save[ ]+152,s0-s1
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3c:[ ]+7080221f[ ]+save[ ]+64,s2
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40:[ ]+7300225f[ ]+save[ ]+72,s2-s7
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44:[ ]+7380229f[ ]+save[ ]+80,s2-s8
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48:[ ]+73802edf[ ]+save[ ]+88,s0-s8
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4c:[ ]+7000a21f[ ]+save[ ]+64,a3
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50:[ ]+7009201f[ ]+save[ ]+128,a2-a3
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54:[ ]+7015a01f[ ]+save[ ]+256,a0-a3
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58:[ ]+7012201f[ ]+save[ ]+a0,256
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5c:[ ]+700c201f[ ]+save[ ]+a0-a1,128
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60:[ ]+7007221f[ ]+save[ ]+a0-a3,64
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64:[ ]+700aa01f[ ]+save[ ]+a0,128,a3
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68:[ ]+700ba01f[ ]+save[ ]+a0,128,a1-a3
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6c:[ ]+700d201f[ ]+save[ ]+a0-a1,128,a2-a3
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70:[ ]+700ea01f[ ]+save[ ]+a0-a2,128,a3
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74:[ ]+738d3c1f[ ]+save[ ]+a0-a1,128,ra,s0-s8,a2-a3
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78:[ ]+70081c1f[ ]+restore[ ]+128,ra,s0-s1
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7c:[ ]+7008105f[ ]+restore[ ]+136,ra
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80:[ ]+7080021f[ ]+restore[ ]+64,s2
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84:[ ]+738d1c1f[ ]+restore[ ]+a0-a1,128,ra,s0-s8,a2-a3
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\.\.\.
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@ -0,0 +1,44 @@
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#objdump: -dr
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#as: -32
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#name: SAVE/RESTORE instructions
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#source: save.s
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.*: +file format .*mips.*
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Disassembly of section .text:
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00000000 <func>:
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0:[ ]+7000205f[ ]+save[ ]+8
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4:[ ]+7000309f[ ]+save[ ]+16,ra
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8:[ ]+700028df[ ]+save[ ]+24,s0
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c:[ ]+7000251f[ ]+save[ ]+32,s1
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10:[ ]+70002d5f[ ]+save[ ]+40,s0-s1
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14:[ ]+7000399f[ ]+save[ ]+48,ra,s0
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18:[ ]+700035df[ ]+save[ ]+56,ra,s1
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1c:[ ]+70003e1f[ ]+save[ ]+64,ra,s0-s1
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20:[ ]+70003e5f[ ]+save[ ]+72,ra,s0-s1
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24:[ ]+70003e9f[ ]+save[ ]+80,ra,s0-s1
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28:[ ]+70003edf[ ]+save[ ]+88,ra,s0-s1
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2c:[ ]+70083c1f[ ]+save[ ]+128,ra,s0-s1
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30:[ ]+7008205f[ ]+save[ ]+136
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34:[ ]+7008309f[ ]+save[ ]+144,ra
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38:[ ]+70082cdf[ ]+save[ ]+152,s0-s1
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3c:[ ]+7080221f[ ]+save[ ]+64,s2
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40:[ ]+7300225f[ ]+save[ ]+72,s2-s7
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44:[ ]+7380229f[ ]+save[ ]+80,s2-s8
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48:[ ]+73802edf[ ]+save[ ]+88,s0-s8
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4c:[ ]+7000a21f[ ]+save[ ]+64,a3
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50:[ ]+7009201f[ ]+save[ ]+128,a2-a3
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54:[ ]+7015a01f[ ]+save[ ]+256,a0-a3
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58:[ ]+7012201f[ ]+save[ ]+a0,256
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5c:[ ]+700c201f[ ]+save[ ]+a0-a1,128
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60:[ ]+7007221f[ ]+save[ ]+a0-a3,64
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64:[ ]+700aa01f[ ]+save[ ]+a0,128,a3
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68:[ ]+700ba01f[ ]+save[ ]+a0,128,a1-a3
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6c:[ ]+700d201f[ ]+save[ ]+a0-a1,128,a2-a3
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70:[ ]+700ea01f[ ]+save[ ]+a0-a2,128,a3
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74:[ ]+738d3c1f[ ]+save[ ]+a0-a1,128,ra,s0-s8,a2-a3
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78:[ ]+70081c1f[ ]+restore[ ]+128,ra,s0-s1
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7c:[ ]+7008105f[ ]+restore[ ]+136,ra
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80:[ ]+7080021f[ ]+restore[ ]+64,s2
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84:[ ]+738d1c1f[ ]+restore[ ]+a0-a1,128,ra,s0-s8,a2-a3
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\.\.\.
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@ -1128,6 +1128,9 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "elf_ase_micromips"
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run_dump_test "elf_ase_micromips-2"
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# Verify that machine markings are handled properly.
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run_dump_test "elf_mach_interaptiv-mr2"
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run_dump_test "mips-gp32-fp32-pic"
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run_dump_test "mips-gp32-fp64-pic"
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run_dump_test "mips-gp64-fp32-pic"
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@ -1382,8 +1385,15 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips64-dsp"
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run_dump_test "mips32-mt"
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run_dump_test_arches "save" [mips_arch_list_matching mips16e-32]
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run_dump_test_arches "save-err" [mips_arch_list_matching mips16e-32]
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run_dump_test_arches "save" [lsort -dictionary -unique [concat \
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[mips_arch_list_matching mips16e-32] \
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[mips_arch_list_matching interaptiv-mr2]]]
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run_dump_test_arches "save-err" [lsort -dictionary -unique [concat \
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[mips_arch_list_matching mips16e-32] \
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[mips_arch_list_matching interaptiv-mr2]]]
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run_dump_test_arches "save-sub" [lsort -dictionary -unique [concat \
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[mips_arch_list_matching mips1 !micromips] \
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[mips_arch_list_matching mips16-32]]]
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run_dump_test "mips16-dwarf2"
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if $has_newabi {
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@ -1393,6 +1403,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips16e-jrc"
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run_dump_test "mips16e2-lui"
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run_dump_test "mips16e2-copy"
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run_dump_test "mips16e2-copy-err"
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run_dump_test "mips16-intermix"
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run_dump_test "mips16-extend"
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@ -0,0 +1,65 @@
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#objdump: -dr
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#as: -32 -I$srcdir/$subdir
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#name: SAVE/RESTORE instruction subset disassembly
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#source: save-sub.s
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.*: +file format .*mips.*
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Disassembly of section .text:
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00000000 <func>:
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0:[ ]+6481[ ]+0x6481
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2:[ ]+64c2[ ]+0x64c2
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4:[ ]+64a3[ ]+0x64a3
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6:[ ]+6494[ ]+0x6494
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8:[ ]+64b5[ ]+0x64b5
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a:[ ]+64e6[ ]+0x64e6
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c:[ ]+64d7[ ]+0x64d7
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e:[ ]+64f8[ ]+0x64f8
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10:[ ]+64f9[ ]+0x64f9
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12:[ ]+64fa[ ]+0x64fa
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14:[ ]+64fb[ ]+0x64fb
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16:[ ]+64f0[ ]+0x64f0
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18:[ ]+f010[ ]+extend[ ]0x10
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1a:[ ]+6481[ ]+0x6481
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1c:[ ]+f010[ ]+extend[ ]0x10
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1e:[ ]+64c2[ ]+0x64c2
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20:[ ]+f010[ ]+extend[ ]0x10
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22:[ ]+64b3[ ]+0x64b3
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24:[ ]+f100[ ]+extend[ ]0x100
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26:[ ]+6488[ ]+0x6488
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28:[ ]+f600[ ]+extend[ ]0x600
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2a:[ ]+6489[ ]+0x6489
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2c:[ ]+f700[ ]+extend[ ]0x700
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2e:[ ]+648a[ ]+0x648a
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30:[ ]+f700[ ]+extend[ ]0x700
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32:[ ]+64bb[ ]+0x64bb
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34:[ ]+f001[ ]+extend[ ]0x1
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36:[ ]+6488[ ]+0x6488
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38:[ ]+f012[ ]+extend[ ]0x12
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3a:[ ]+6480[ ]+0x6480
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3c:[ ]+f02b[ ]+extend[ ]0x2b
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3e:[ ]+6480[ ]+0x6480
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40:[ ]+f024[ ]+extend[ ]0x24
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42:[ ]+6480[ ]+0x6480
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44:[ ]+f018[ ]+extend[ ]0x18
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46:[ ]+6480[ ]+0x6480
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48:[ ]+f00e[ ]+extend[ ]0xe
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4a:[ ]+6488[ ]+0x6488
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4c:[ ]+f015[ ]+extend[ ]0x15
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4e:[ ]+6480[ ]+0x6480
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50:[ ]+f017[ ]+extend[ ]0x17
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52:[ ]+6480[ ]+0x6480
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54:[ ]+f01a[ ]+extend[ ]0x1a
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56:[ ]+6480[ ]+0x6480
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58:[ ]+f01d[ ]+extend[ ]0x1d
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5a:[ ]+6480[ ]+0x6480
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5c:[ ]+f71a[ ]+extend[ ]0x71a
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5e:[ ]+64f0[ ]+0x64f0
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60:[ ]+6470[ ]+0x6470
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62:[ ]+f010[ ]+extend[ ]0x10
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64:[ ]+6441[ ]+0x6441
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66:[ ]+f100[ ]+extend[ ]0x100
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68:[ ]+6408[ ]+0x6408
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6a:[ ]+f71a[ ]+extend[ ]0x71a
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6c:[ ]+6470[ ]+0x6470
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\.\.\.
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@ -0,0 +1,3 @@
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#name: MIPS16e2 interAptiv MR2 COPYW/UCOPYW ASMACRO instruction errors
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#as: -32 -mips16 -march=interaptiv-mr2
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#error-output: mips16e2-copy-err.l
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.*: Assembler messages:
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.*:5: Error: operand 4 out of range `copyw \$2,\$2,0,0'
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.*:6: Error: operand 4 out of range `copyw \$2,\$2,0,5'
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.*:7: Error: operand 3 out of range `copyw \$2,\$2,-16,1'
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.*:8: Error: operand 3 out of range `copyw \$2,\$2,-15,1'
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.*:9: Error: operand 3 out of range `copyw \$2,\$2,-1,1'
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.*:10: Error: operand 3 out of range `copyw \$2,\$2,1,1'
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.*:11: Error: operand 3 out of range `copyw \$2,\$2,15,1'
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.*:12: Error: operand 3 out of range `copyw \$2,\$2,512,1'
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.*:13: Error: invalid operands `copyw \$2,\$1,0,1'
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.*:14: Error: invalid operands `copyw \$2,\$8,0,1'
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.*:15: Error: invalid operands `copyw \$1,\$2,0,1'
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.*:16: Error: invalid operands `copyw \$8,\$2,0,1'
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.*:17: Error: operand 3 out of range `copyw \$2,\$2,1,0'
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.*:18: Error: invalid operands `copyw \$8,\$1,1,0'
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.*:19: Error: operand 4 out of range `ucopyw \$2,\$2,0,0'
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.*:20: Error: operand 4 out of range `ucopyw \$2,\$2,0,5'
|
||||
.*:21: Error: operand 3 out of range `ucopyw \$2,\$2,-16,1'
|
||||
.*:22: Error: operand 3 out of range `ucopyw \$2,\$2,-15,1'
|
||||
.*:23: Error: operand 3 out of range `ucopyw \$2,\$2,-1,1'
|
||||
.*:24: Error: operand 3 out of range `ucopyw \$2,\$2,1,1'
|
||||
.*:25: Error: operand 3 out of range `ucopyw \$2,\$2,15,1'
|
||||
.*:26: Error: operand 3 out of range `ucopyw \$2,\$2,512,1'
|
||||
.*:27: Error: invalid operands `ucopyw \$2,\$1,0,1'
|
||||
.*:28: Error: invalid operands `ucopyw \$2,\$8,0,1'
|
||||
.*:29: Error: invalid operands `ucopyw \$1,\$2,0,1'
|
||||
.*:30: Error: invalid operands `ucopyw \$8,\$2,0,1'
|
||||
.*:31: Error: operand 3 out of range `ucopyw \$2,\$2,1,0'
|
||||
.*:32: Error: invalid operands `ucopyw \$8,\$1,1,0'
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# Verify interAptiv MR2 MIPS16e2 COPYW/UCOPYW ASMACRO instruction errors.
|
||||
|
||||
.text
|
||||
foo:
|
||||
copyw $2, $2, 0, 0
|
||||
copyw $2, $2, 0, 5
|
||||
copyw $2, $2, -16, 1
|
||||
copyw $2, $2, -15, 1
|
||||
copyw $2, $2, -1, 1
|
||||
copyw $2, $2, 1, 1
|
||||
copyw $2, $2, 15, 1
|
||||
copyw $2, $2, 512, 1
|
||||
copyw $2, $1, 0, 1
|
||||
copyw $2, $8, 0, 1
|
||||
copyw $1, $2, 0, 1
|
||||
copyw $8, $2, 0, 1
|
||||
copyw $2, $2, 1, 0
|
||||
copyw $8, $1, 1, 0
|
||||
ucopyw $2, $2, 0, 0
|
||||
ucopyw $2, $2, 0, 5
|
||||
ucopyw $2, $2, -16, 1
|
||||
ucopyw $2, $2, -15, 1
|
||||
ucopyw $2, $2, -1, 1
|
||||
ucopyw $2, $2, 1, 1
|
||||
ucopyw $2, $2, 15, 1
|
||||
ucopyw $2, $2, 512, 1
|
||||
ucopyw $2, $1, 0, 1
|
||||
ucopyw $2, $8, 0, 1
|
||||
ucopyw $1, $2, 0, 1
|
||||
ucopyw $8, $2, 0, 1
|
||||
ucopyw $2, $2, 1, 0
|
||||
ucopyw $8, $1, 1, 0
|
||||
|
||||
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 16
|
||||
.align 4, 0
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: MIPS16e2 interAptiv MR2 COPYW/UCOPYW ASMACRO instructions
|
||||
#as: -32 -mips16 -march=interaptiv-mr2
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> f020 e260 copyw v0,v1,0,1
|
||||
[0-9a-f]+ <[^>]*> f021 e381 copyw v1,a0,16,2
|
||||
[0-9a-f]+ <[^>]*> f022 e4a2 copyw a0,a1,32,3
|
||||
[0-9a-f]+ <[^>]*> f024 e5c3 copyw a1,a2,64,4
|
||||
[0-9a-f]+ <[^>]*> f028 e6e0 copyw a2,a3,128,1
|
||||
[0-9a-f]+ <[^>]*> f030 e701 copyw a3,s0,256,2
|
||||
[0-9a-f]+ <[^>]*> f038 e022 copyw s0,s1,384,3
|
||||
[0-9a-f]+ <[^>]*> f03c e143 copyw s1,v0,448,4
|
||||
[0-9a-f]+ <[^>]*> f03e e260 copyw v0,v1,480,1
|
||||
[0-9a-f]+ <[^>]*> f03f e381 copyw v1,a0,496,2
|
||||
[0-9a-f]+ <[^>]*> f02a e4a2 copyw a0,a1,160,3
|
||||
[0-9a-f]+ <[^>]*> f035 e5c3 copyw a1,a2,336,4
|
||||
[0-9a-f]+ <[^>]*> f000 e6e0 ucopyw a2,a3,0,1
|
||||
[0-9a-f]+ <[^>]*> f001 e701 ucopyw a3,s0,16,2
|
||||
[0-9a-f]+ <[^>]*> f002 e022 ucopyw s0,s1,32,3
|
||||
[0-9a-f]+ <[^>]*> f004 e143 ucopyw s1,v0,64,4
|
||||
[0-9a-f]+ <[^>]*> f008 e260 ucopyw v0,v1,128,1
|
||||
[0-9a-f]+ <[^>]*> f010 e381 ucopyw v1,a0,256,2
|
||||
[0-9a-f]+ <[^>]*> f018 e4a2 ucopyw a0,a1,384,3
|
||||
[0-9a-f]+ <[^>]*> f01c e5c3 ucopyw a1,a2,448,4
|
||||
[0-9a-f]+ <[^>]*> f01e e6e0 ucopyw a2,a3,480,1
|
||||
[0-9a-f]+ <[^>]*> f01f e701 ucopyw a3,s0,496,2
|
||||
[0-9a-f]+ <[^>]*> f00a e022 ucopyw s0,s1,160,3
|
||||
[0-9a-f]+ <[^>]*> f015 e143 ucopyw s1,v0,336,4
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
# Verify the interAptiv MR2 MIPS16e2 COPYW/UCOPYW ASMACRO instructions.
|
||||
|
||||
.text
|
||||
foo:
|
||||
copyw $2, $3, 0, 1
|
||||
copyw $3, $4, 16, 2
|
||||
copyw $4, $5, 32, 3
|
||||
copyw $5, $6, 64, 4
|
||||
copyw $6, $7, 128, 1
|
||||
copyw $7, $16, 256, 2
|
||||
copyw $16, $17, 384, 3
|
||||
copyw $17, $2, 448, 4
|
||||
copyw $2, $3, 480, 1
|
||||
copyw $3, $4, 496, 2
|
||||
copyw $4, $5, 160, 3
|
||||
copyw $5, $6, 336, 4
|
||||
ucopyw $6, $7, 0, 1
|
||||
ucopyw $7, $16, 16, 2
|
||||
ucopyw $16, $17, 32, 3
|
||||
ucopyw $17, $2, 64, 4
|
||||
ucopyw $2, $3, 128, 1
|
||||
ucopyw $3, $4, 256, 2
|
||||
ucopyw $4, $5, 384, 3
|
||||
ucopyw $5, $6, 448, 4
|
||||
ucopyw $6, $7, 480, 1
|
||||
ucopyw $7, $16, 496, 2
|
||||
ucopyw $16, $17, 160, 3
|
||||
ucopyw $17, $2, 336, 4
|
||||
|
||||
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 16
|
||||
.align 4, 0
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
00000000 <func>:
|
||||
0:[ ]+6481[ ]+save[ ]+8
|
||||
2:[ ]+64c2[ ]+save[ ]+16,ra
|
||||
4:[ ]+64a3[ ]+save[ ]+24,s0
|
||||
6:[ ]+6494[ ]+save[ ]+32,s1
|
||||
8:[ ]+64b5[ ]+save[ ]+40,s0-s1
|
||||
a:[ ]+64e6[ ]+save[ ]+48,ra,s0
|
||||
c:[ ]+64d7[ ]+save[ ]+56,ra,s1
|
||||
e:[ ]+64f8[ ]+save[ ]+64,ra,s0-s1
|
||||
10:[ ]+64f9[ ]+save[ ]+72,ra,s0-s1
|
||||
12:[ ]+64fa[ ]+save[ ]+80,ra,s0-s1
|
||||
14:[ ]+64fb[ ]+save[ ]+88,ra,s0-s1
|
||||
16:[ ]+64f0[ ]+save[ ]+128,ra,s0-s1
|
||||
18:[ ]+f010 6481[ ]+save[ ]+136
|
||||
1c:[ ]+f010 64c2[ ]+save[ ]+144,ra
|
||||
20:[ ]+f010 64b3[ ]+save[ ]+152,s0-s1
|
||||
24:[ ]+f100 6488[ ]+save[ ]+64,s2
|
||||
28:[ ]+f600 6489[ ]+save[ ]+72,s2-s7
|
||||
2c:[ ]+f700 648a[ ]+save[ ]+80,s2-s8
|
||||
30:[ ]+f700 64bb[ ]+save[ ]+88,s0-s8
|
||||
34:[ ]+f001 6488[ ]+save[ ]+64,a3
|
||||
38:[ ]+f012 6480[ ]+save[ ]+128,a2-a3
|
||||
3c:[ ]+f02b 6480[ ]+save[ ]+256,a0-a3
|
||||
40:[ ]+f024 6480[ ]+save[ ]+a0,256
|
||||
44:[ ]+f018 6480[ ]+save[ ]+a0-a1,128
|
||||
48:[ ]+f00e 6488[ ]+save[ ]+a0-a3,64
|
||||
4c:[ ]+f015 6480[ ]+save[ ]+a0,128,a3
|
||||
50:[ ]+f017 6480[ ]+save[ ]+a0,128,a1-a3
|
||||
54:[ ]+f01a 6480[ ]+save[ ]+a0-a1,128,a2-a3
|
||||
58:[ ]+f01d 6480[ ]+save[ ]+a0-a2,128,a3
|
||||
5c:[ ]+f71a 64f0[ ]+save[ ]+a0-a1,128,ra,s0-s8,a2-a3
|
||||
60:[ ]+6470[ ]+restore[ ]+128,ra,s0-s1
|
||||
62:[ ]+f010 6441[ ]+restore[ ]+136,ra
|
||||
66:[ ]+f100 6408[ ]+restore[ ]+64,s2
|
||||
6a:[ ]+f71a 6470[ ]+restore[ ]+a0-a1,128,ra,s0-s8,a2-a3
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
00000000 <func>:
|
||||
0:[ ]+7000205f[ ]+0x7000205f
|
||||
4:[ ]+7000309f[ ]+0x7000309f
|
||||
8:[ ]+700028df[ ]+0x700028df
|
||||
c:[ ]+7000251f[ ]+0x7000251f
|
||||
10:[ ]+70002d5f[ ]+0x70002d5f
|
||||
14:[ ]+7000399f[ ]+0x7000399f
|
||||
18:[ ]+700035df[ ]+0x700035df
|
||||
1c:[ ]+70003e1f[ ]+0x70003e1f
|
||||
20:[ ]+70003e5f[ ]+0x70003e5f
|
||||
24:[ ]+70003e9f[ ]+0x70003e9f
|
||||
28:[ ]+70003edf[ ]+0x70003edf
|
||||
2c:[ ]+70083c1f[ ]+0x70083c1f
|
||||
30:[ ]+7008205f[ ]+0x7008205f
|
||||
34:[ ]+7008309f[ ]+0x7008309f
|
||||
38:[ ]+70082cdf[ ]+0x70082cdf
|
||||
3c:[ ]+7080221f[ ]+0x7080221f
|
||||
40:[ ]+7300225f[ ]+0x7300225f
|
||||
44:[ ]+7380229f[ ]+0x7380229f
|
||||
48:[ ]+73802edf[ ]+0x73802edf
|
||||
4c:[ ]+7000a21f[ ]+0x7000a21f
|
||||
50:[ ]+7009201f[ ]+0x7009201f
|
||||
54:[ ]+7015a01f[ ]+0x7015a01f
|
||||
58:[ ]+7012201f[ ]+0x7012201f
|
||||
5c:[ ]+700c201f[ ]+0x700c201f
|
||||
60:[ ]+7007221f[ ]+0x7007221f
|
||||
64:[ ]+700aa01f[ ]+0x700aa01f
|
||||
68:[ ]+700ba01f[ ]+0x700ba01f
|
||||
6c:[ ]+700d201f[ ]+0x700d201f
|
||||
70:[ ]+700ea01f[ ]+0x700ea01f
|
||||
74:[ ]+738d3c1f[ ]+0x738d3c1f
|
||||
78:[ ]+70081c1f[ ]+0x70081c1f
|
||||
7c:[ ]+7008105f[ ]+0x7008105f
|
||||
80:[ ]+7080021f[ ]+0x7080021f
|
||||
84:[ ]+738d1c1f[ ]+0x738d1c1f
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
00000000 <func>:
|
||||
0:[ ]+7000205f[ ]+udi15[ ]+zero,zero,a0,0x1
|
||||
4:[ ]+7000309f[ ]+lai[ ]+a2,\(zero\)
|
||||
8:[ ]+700028df[ ]+laid[ ]+a1,\(zero\)
|
||||
c:[ ]+7000251f[ ]+udi15[ ]+zero,zero,a0,0x14
|
||||
10:[ ]+70002d5f[ ]+udi15[ ]+zero,zero,a1,0x15
|
||||
14:[ ]+7000399f[ ]+lad[ ]+a3,\(zero\)
|
||||
18:[ ]+700035df[ ]+lawd[ ]+a2,\(zero\),zero
|
||||
1c:[ ]+70003e1f[ ]+udi15[ ]+zero,zero,a3,0x18
|
||||
20:[ ]+70003e5f[ ]+udi15[ ]+zero,zero,a3,0x19
|
||||
24:[ ]+70003e9f[ ]+udi15[ ]+zero,zero,a3,0x1a
|
||||
28:[ ]+70003edf[ ]+udi15[ ]+zero,zero,a3,0x1b
|
||||
2c:[ ]+70083c1f[ ]+udi15[ ]+zero,t0,a3,0x10
|
||||
30:[ ]+7008205f[ ]+udi15[ ]+zero,t0,a0,0x1
|
||||
34:[ ]+7008309f[ ]+udi15[ ]+zero,t0,a2,0x2
|
||||
38:[ ]+70082cdf[ ]+laad[ ]+a1,\(zero\),t0
|
||||
3c:[ ]+7080221f[ ]+udi15[ ]+a0,zero,a0,0x8
|
||||
40:[ ]+7300225f[ ]+udi15[ ]+t8,zero,a0,0x9
|
||||
44:[ ]+7380229f[ ]+las[ ]+a0,\(gp\)
|
||||
48:[ ]+73802edf[ ]+udi15[ ]+gp,zero,a1,0x1b
|
||||
4c:[ ]+7000a21f[ ]+udi15[ ]+zero,zero,s4,0x8
|
||||
50:[ ]+7009201f[ ]+udi15[ ]+zero,t1,a0,0x0
|
||||
54:[ ]+7015a01f[ ]+udi15[ ]+zero,s5,s4,0x0
|
||||
58:[ ]+7012201f[ ]+udi15[ ]+zero,s2,a0,0x0
|
||||
5c:[ ]+700c201f[ ]+udi15[ ]+zero,t4,a0,0x0
|
||||
60:[ ]+7007221f[ ]+udi15[ ]+zero,a3,a0,0x8
|
||||
64:[ ]+700aa01f[ ]+udi15[ ]+zero,t2,s4,0x0
|
||||
68:[ ]+700ba01f[ ]+udi15[ ]+zero,t3,s4,0x0
|
||||
6c:[ ]+700d201f[ ]+udi15[ ]+zero,t5,a0,0x0
|
||||
70:[ ]+700ea01f[ ]+udi15[ ]+zero,t6,s4,0x0
|
||||
74:[ ]+738d3c1f[ ]+udi15[ ]+gp,t5,a3,0x10
|
||||
78:[ ]+70081c1f[ ]+udi15[ ]+zero,t0,v1,0x10
|
||||
7c:[ ]+7008105f[ ]+udi15[ ]+zero,t0,v0,0x1
|
||||
80:[ ]+7080021f[ ]+udi15[ ]+a0,zero,zero,0x8
|
||||
84:[ ]+738d1c1f[ ]+udi15[ ]+gp,t5,v1,0x10
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: octeon2@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
#name: MIPS16e SAVE/RESTORE errors
|
||||
#name: SAVE/RESTORE instruction errors
|
||||
#as: -32
|
||||
#error-output: save-err.l
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
00000000 <func>:
|
||||
0:[ ]+7000205f[ ]+udi15[ ]+zero,zero,a0,0x1
|
||||
4:[ ]+7000309f[ ]+udi15[ ]+zero,zero,a2,0x2
|
||||
8:[ ]+700028df[ ]+udi15[ ]+zero,zero,a1,0x3
|
||||
c:[ ]+7000251f[ ]+udi15[ ]+zero,zero,a0,0x14
|
||||
10:[ ]+70002d5f[ ]+udi15[ ]+zero,zero,a1,0x15
|
||||
14:[ ]+7000399f[ ]+udi15[ ]+zero,zero,a3,0x6
|
||||
18:[ ]+700035df[ ]+udi15[ ]+zero,zero,a2,0x17
|
||||
1c:[ ]+70003e1f[ ]+udi15[ ]+zero,zero,a3,0x18
|
||||
20:[ ]+70003e5f[ ]+udi15[ ]+zero,zero,a3,0x19
|
||||
24:[ ]+70003e9f[ ]+udi15[ ]+zero,zero,a3,0x1a
|
||||
28:[ ]+70003edf[ ]+udi15[ ]+zero,zero,a3,0x1b
|
||||
2c:[ ]+70083c1f[ ]+udi15[ ]+zero,t0,a3,0x10
|
||||
30:[ ]+7008205f[ ]+udi15[ ]+zero,t0,a0,0x1
|
||||
34:[ ]+7008309f[ ]+udi15[ ]+zero,t0,a2,0x2
|
||||
38:[ ]+70082cdf[ ]+udi15[ ]+zero,t0,a1,0x13
|
||||
3c:[ ]+7080221f[ ]+udi15[ ]+a0,zero,a0,0x8
|
||||
40:[ ]+7300225f[ ]+udi15[ ]+t8,zero,a0,0x9
|
||||
44:[ ]+7380229f[ ]+udi15[ ]+gp,zero,a0,0xa
|
||||
48:[ ]+73802edf[ ]+udi15[ ]+gp,zero,a1,0x1b
|
||||
4c:[ ]+7000a21f[ ]+udi15[ ]+zero,zero,s4,0x8
|
||||
50:[ ]+7009201f[ ]+udi15[ ]+zero,t1,a0,0x0
|
||||
54:[ ]+7015a01f[ ]+udi15[ ]+zero,s5,s4,0x0
|
||||
58:[ ]+7012201f[ ]+udi15[ ]+zero,s2,a0,0x0
|
||||
5c:[ ]+700c201f[ ]+udi15[ ]+zero,t4,a0,0x0
|
||||
60:[ ]+7007221f[ ]+udi15[ ]+zero,a3,a0,0x8
|
||||
64:[ ]+700aa01f[ ]+udi15[ ]+zero,t2,s4,0x0
|
||||
68:[ ]+700ba01f[ ]+udi15[ ]+zero,t3,s4,0x0
|
||||
6c:[ ]+700d201f[ ]+udi15[ ]+zero,t5,a0,0x0
|
||||
70:[ ]+700ea01f[ ]+udi15[ ]+zero,t6,s4,0x0
|
||||
74:[ ]+738d3c1f[ ]+udi15[ ]+gp,t5,a3,0x10
|
||||
78:[ ]+70081c1f[ ]+udi15[ ]+zero,t0,v1,0x10
|
||||
7c:[ ]+7008105f[ ]+udi15[ ]+zero,t0,v0,0x1
|
||||
80:[ ]+7080021f[ ]+udi15[ ]+a0,zero,zero,0x8
|
||||
84:[ ]+738d1c1f[ ]+udi15[ ]+gp,t5,v1,0x10
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
.set arch=interaptiv-mr2
|
||||
.include "save.s"
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#objdump: -dr
|
||||
#as: -32
|
||||
#name: MIPS16e SAVE/RESTORE
|
||||
#name: SAVE/RESTORE instructions
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
|
|
@ -40,4 +40,4 @@ Disassembly of section .text:
|
|||
62:[ ]+f010 6441[ ]+restore[ ]+136,ra
|
||||
66:[ ]+f100 6408[ ]+restore[ ]+64,s2
|
||||
6a:[ ]+f71a 6470[ ]+restore[ ]+a0-a1,128,ra,s0-s8,a2-a3
|
||||
6e:[ ]+6500[ ]+nop
|
||||
\.\.\.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Test the generation of the mips16e save instruction
|
||||
# Test the generation of the SAVE/RESTORE instructions.
|
||||
|
||||
.text
|
||||
func:
|
||||
|
|
@ -26,7 +26,7 @@ func:
|
|||
save $18-$23,72
|
||||
save $18-$23,$30,80
|
||||
save $16-$23,$30,88
|
||||
|
||||
|
||||
# static areg
|
||||
save 64,$7
|
||||
save 128,$7,$6
|
||||
|
|
@ -49,6 +49,5 @@ func:
|
|||
restore $31,136
|
||||
restore $18,64
|
||||
restore $4-$5,$16-$23,$30-$31,128,$6-$7
|
||||
|
||||
.p2align 4
|
||||
|
||||
.p2align 4, 0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2
|
||||
tests.
|
||||
|
||||
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
|
||||
|
||||
PR ld/13402
|
||||
|
|
|
|||
|
|
@ -199,6 +199,17 @@ isa_conflict { "-march=r5900 -32" "-march=vr4111 -32" } 5900 4111
|
|||
isa_conflict { "-march=loongson2e -32" "-march=loongson2f -32" } loongson_2e loongson_2f
|
||||
isa_conflict { "-march=loongson3a -32" "-march=loongson2f -32" } loongson_3a loongson_2f
|
||||
|
||||
isa_conflict { "-march=interaptiv-mr2 -32" \
|
||||
"-march=r4010 -32" } interaptiv-mr2 4010
|
||||
isa_conflict { "-march=interaptiv-mr2 -mnan=2008 -mfp64 -32" \
|
||||
"-mips32r6 -32" } interaptiv-mr2 isa32r6
|
||||
isa_conflict { "-march=interaptiv-mr2 -32" \
|
||||
"-mips3 -32" } interaptiv-mr2 4000
|
||||
isa_conflict { "-march=interaptiv-mr2 -32" \
|
||||
"-mips64r2 -32" } interaptiv-mr2 isa64r2
|
||||
isa_conflict { "-march=interaptiv-mr2 -32" \
|
||||
"-march=octeon -32" } interaptiv-mr2 octeon
|
||||
|
||||
regsize_conflict { "-mips4 -mgp64 -mabi=o64" "-mips2 -32" }
|
||||
regsize_conflict { "-mips4 -mabi=o64" "-mips4 -mabi=32" }
|
||||
regsize_conflict { "-mips4 -mabi=eabi -mgp32" "-mips4 -mabi=eabi -mgp64" }
|
||||
|
|
@ -225,3 +236,37 @@ good_combination { "-march=sb1 -mgp32 -32" "-march=4000 -mgp32 -32" } { sb1 o3
|
|||
good_combination { "-mips32 -mabi=32" "-march=sb1 -mabi=32" } { sb1 o32 }
|
||||
good_combination { "-mips64r2 -mabi=32" "-mips32 -mabi=32" } { mips64r2 o32 }
|
||||
good_combination { "-mips5 -mabi=o64" "-mips64r2 -mabi=o64" } { mips64r2 o64 }
|
||||
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-mips1 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-mips32r2 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-march=interaptiv -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-mips32r3 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-mips32r3 -mips16 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" "MIPS16 ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -mips16 -32" "-mips32r3 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r3 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" \
|
||||
"MIPS16 ASE" "MIPS16e2 ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-mips32r5 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r5 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \
|
||||
{ mips32r2 interaptiv-mr2 } \
|
||||
MIPS32r5 "Imagination interAptiv MR2" \
|
||||
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
|
||||
|
|
|
|||
Loading…
Reference in New Issue