* sim-main.h: Delete inclusion of config.h, include sim-basics.h
before cgen-types.h. * tconfig.in: Guard against multiple inclusion. * cpu.h: Delete decls moved to genmloop.sh. * cpux.h: Ditto.
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@ -1,3 +1,13 @@
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Wed Nov 4 23:55:37 1998 Doug Evans <devans@seba.cygnus.com>
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* sim-main.h: Delete inclusion of config.h, include sim-basics.h
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before cgen-types.h.
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* tconfig.in: Guard against multiple inclusion.
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* cpu.h: Delete decls moved to genmloop.sh.
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start-sanitize-m32rx
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* cpux.h: Ditto.
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end-sanitize-m32rx
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Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
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Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
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* sim-main.h: #include cpu-opc.h.
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* sim-main.h: #include cpu-opc.h.
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717
sim/m32r/cpu.h
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sim/m32r/cpu.h
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sim/m32r/cpux.h
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sim/m32r/cpux.h
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/* M32R target configuration file. -*- C -*- */
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/* M32R target configuration file. -*- C -*- */
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#ifndef M32R_TCONFIG_H
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#define M32R_TCONFIG_H
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/* Define this if the simulator can vary the size of memory.
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/* Define this if the simulator can vary the size of memory.
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See the xxx simulator for an example.
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See the xxx simulator for an example.
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This enables the `-m size' option.
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This enables the `-m size' option.
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/* Not used for M32R since we use the memory module. */
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/* Not used for M32R since we use the memory module. */
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/* #define SIM_HAVE_MEM_SIZE */
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/* #define SIM_HAVE_MEM_SIZE */
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/* See sim-hload.c. We properly handle LMA. */
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#define SIM_HANDLES_LMA 1
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/* For MSPR support. FIXME: revisit. */
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/* For MSPR support. FIXME: revisit. */
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#define WITH_DEVICES 1
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#define WITH_DEVICES 1
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/* The semantic code should probably always use a switch().
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/* FIXME: Revisit. */
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However, in case that's not possible in some circumstance, we allow
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#ifdef HAVE_DV_SOCKSER
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the target to choose. Perhaps this can be autoconf'd on whether the
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MODULE_INSTALL_FN dv_sockser_install;
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switch is too big? I can't (yet) think of a reason for allowing the
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#define MODULE_LIST dv_sockser_install,
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user to choose, though the developer may certainly wish to. */
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#ifdef WANT_CPU_M32R
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#define WITH_FAST 1
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#define WITH_SEM_SWITCH_FULL 0
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#define WITH_SEM_SWITCH_FAST 1
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#endif
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#endif
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#ifdef WANT_CPU_M32RX
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#if 0
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#define HAVE_PARALLEL_EXEC
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/* Enable watchpoints. */
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#define WITH_FAST 0
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#define WITH_WATCHPOINTS 1
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#define WITH_SEM_SWITCH_FULL 1
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#define WITH_SEM_SWITCH_FAST 0
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/* The m32rx currently never uses the scache. So hardcode this off. */
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#undef WITH_SCACHE
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#define WITH_SCACHE 0
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#endif
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#endif
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/* ??? Temporary hack until model support unified. */
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/* ??? Temporary hack until model support unified. */
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#define SIM_HAVE_MODEL
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#define SIM_HAVE_MODEL
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/* Define this to enable the intrinsic breakpoint mechanism. */
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/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
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duplicates ifdef SIM_BREAKPOINT (right?) */
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#if 0
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#define SIM_HAVE_BREAKPOINTS
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#define SIM_BREAKPOINT { 0x10, 0xf1 }
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#define SIM_BREAKPOINT_SIZE 2
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#endif
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/* This is a global setting. Different cpu families can't mix-n-match -scache
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and -bb. However some cpu families may use -simple while others use
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one of -scache/-bb. */
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#define WITH_SCACHE_PBB 1
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#endif /* M32R_TCONFIG_H */
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