MIPS: Add microMIPS XPA support
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
This commit is contained in:
Maciej W. Rozycki
parent
f5b2fd523f
commit
909b4e3d5f
|
|
@ -1,3 +1,7 @@
|
|||
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* NEWS: Mention microMIPS XPA support.
|
||||
|
||||
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* NEWS: Mention microMIPS Release 5 ISA support.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,8 @@
|
|||
-*- text -*-
|
||||
|
||||
* The MIPS port now supports microMIPS eXtended Physical Addressing (XPA)
|
||||
instructions for assembly and disassembly.
|
||||
|
||||
* The MIPS port now supports the microMIPS Release 5 ISA for assembly and
|
||||
disassembly.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||||
Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
|
||||
* testsuite/gas/mips/micromips@xpa.d: New test.
|
||||
* testsuite/gas/mips/mips.exp: Run the new test. Enable
|
||||
`xpa-virt-err' test for `micromips'.
|
||||
|
||||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||||
Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -1762,7 +1762,7 @@ static const struct mips_ase mips_ases[] = {
|
|||
|
||||
{ "xpa", ASE_XPA, 0,
|
||||
OPTION_XPA, OPTION_NO_XPA,
|
||||
2, 2, -1, -1,
|
||||
2, 2, 2, 2,
|
||||
-1 },
|
||||
|
||||
{ "mips16e2", ASE_MIPS16E2, 0,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32r2
|
||||
#name: XPA instructions
|
||||
#source: xpa.s
|
||||
#as: -32 -mxpa -mvirt
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> 0041 00f4 mfhc0 v0,c0_random
|
||||
[0-9a-f]+ <[^>]*> 0050 00f4 mfhc0 v0,c0_config
|
||||
[0-9a-f]+ <[^>]*> 0040 10f4 mfhc0 v0,c0_mvpconf0
|
||||
[0-9a-f]+ <[^>]*> 0040 38f4 mfhc0 v0,\$0,7
|
||||
[0-9a-f]+ <[^>]*> 0041 02f4 mthc0 v0,c0_random
|
||||
[0-9a-f]+ <[^>]*> 0050 02f4 mthc0 v0,c0_config
|
||||
[0-9a-f]+ <[^>]*> 0040 12f4 mthc0 v0,c0_mvpconf0
|
||||
[0-9a-f]+ <[^>]*> 0040 3af4 mthc0 v0,\$0,7
|
||||
[0-9a-f]+ <[^>]*> 0041 04f4 mfhgc0 v0,c0_random
|
||||
[0-9a-f]+ <[^>]*> 0050 04f4 mfhgc0 v0,c0_config
|
||||
[0-9a-f]+ <[^>]*> 0040 14f4 mfhgc0 v0,c0_mvpconf0
|
||||
[0-9a-f]+ <[^>]*> 0040 3cf4 mfhgc0 v0,\$0,7
|
||||
[0-9a-f]+ <[^>]*> 0041 06f4 mthgc0 v0,c0_random
|
||||
[0-9a-f]+ <[^>]*> 0050 06f4 mthgc0 v0,c0_config
|
||||
[0-9a-f]+ <[^>]*> 0040 16f4 mthgc0 v0,c0_mvpconf0
|
||||
[0-9a-f]+ <[^>]*> 0040 3ef4 mthgc0 v0,\$0,7
|
||||
\.\.\.
|
||||
|
|
@ -1561,10 +1561,9 @@ if { [istarget mips*-*-vxworks*] } {
|
|||
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2 !mips32r6]
|
||||
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
|
||||
|
||||
run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
|
||||
run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2 !micromips]
|
||||
run_dump_test_arches "xpa-virt-err" \
|
||||
[mips_arch_list_matching mips32r2 !micromips]
|
||||
run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "xpa-virt-err" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5]
|
||||
|
||||
run_dump_test "pcrel-1"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||||
Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
* micromips-opc.c (XPA, XPAVZ): New macros.
|
||||
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
|
||||
"mthgc0".
|
||||
|
||||
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
|
||||
Maciej W. Rozycki <macro@imgtec.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -280,6 +280,10 @@ decode_micromips_operand (const char *p)
|
|||
#define MSA ASE_MSA
|
||||
#define MSA64 ASE_MSA64
|
||||
|
||||
/* eXtended Physical Address (XPA) support. */
|
||||
#define XPA ASE_XPA
|
||||
#define XPAVZ ASE_XPA_VIRT
|
||||
|
||||
const struct mips_opcode micromips_opcodes[] =
|
||||
{
|
||||
/* These instructions appear first so that the disassembler will find
|
||||
|
|
@ -835,6 +839,10 @@ const struct mips_opcode micromips_opcodes[] =
|
|||
{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
|
||||
{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
|
||||
{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
|
||||
{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 },
|
||||
{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 },
|
||||
{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
|
||||
{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
|
||||
{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
|
||||
{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
|
||||
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
|
||||
|
|
@ -881,6 +889,10 @@ const struct mips_opcode micromips_opcodes[] =
|
|||
{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
|
||||
{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
|
||||
{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
|
||||
{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
|
||||
{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
|
||||
{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
|
||||
{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
|
||||
{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
|
||||
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
|
||||
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue