[PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a]
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function. (do_mve_vmaxnma_vminnma): Likewise. (do_neon_dyadic_if_su): Change to support MVE variants. (do_vmaxnm): Likewise. (insns): Change to accept MVE variants and add new. * testsuite/gas/arm/mve-vmax-vmin-bad.d: New test. * testsuite/gas/arm/mve-vmax-vmin-bad.l: New test. * testsuite/gas/arm/mve-vmax-vmin-bad.s: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
7df5412033
commit
935295b51d
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@ -1,3 +1,23 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.
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(do_mve_vmaxnma_vminnma): Likewise.
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(do_neon_dyadic_if_su): Change to support MVE variants.
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(do_vmaxnm): Likewise.
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(insns): Change to accept MVE variants and add new.
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* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.
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* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.
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* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.
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* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.
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* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.
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* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.
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* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.
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* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.
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* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.
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* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.
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* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.
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* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): New operand.
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@ -15590,6 +15590,26 @@ do_mve_vcmp (void)
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return;
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}
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static void
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do_mve_vmaxa_vmina (void)
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{
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (et.size) << 18;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.is_neon = 1;
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}
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static void
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do_mve_vfmas (void)
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{
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@ -15659,6 +15679,26 @@ do_mve_viddup (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vmaxnma_vminnma (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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inst.instruction |= (et.size == 16) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.is_neon = 1;
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}
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static void
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do_mve_vcmul (void)
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{
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@ -16701,6 +16741,11 @@ do_neon_dyadic_if_su (void)
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struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
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N_SUF_32 | N_KEY);
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constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
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|| inst.instruction == ((unsigned) N_MNEM_vmin))
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&& et.type == NT_float
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&& !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
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if (check_simd_pred_availability (et.type == NT_float,
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NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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@ -19743,12 +19788,13 @@ do_vsel (void)
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static void
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do_vmaxnm (void)
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{
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set_pred_insn_type (OUTSIDE_PRED_INSN);
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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set_pred_insn_type (OUTSIDE_PRED_INSN);
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if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
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return;
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
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if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH8))
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return;
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neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
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@ -22951,8 +22997,6 @@ static const struct asm_opcode insns[] =
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nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
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nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
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nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
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nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
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nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
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@ -23671,9 +23715,7 @@ static const struct asm_opcode insns[] =
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NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
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/* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
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nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
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nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
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nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
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nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
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nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
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/* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
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back to neon_dyadic_if_su. */
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@ -24370,11 +24412,15 @@ static const struct asm_opcode insns[] =
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mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
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mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
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mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
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mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1
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@ -24418,6 +24464,8 @@ static const struct asm_opcode insns[] =
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mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
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mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
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mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
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mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
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mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_neon_ext_v1
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@ -24436,6 +24484,8 @@ static const struct asm_opcode insns[] =
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MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
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MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
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MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
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mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
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mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VMAX and VMIN instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmax-vmin-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,27 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmax.s64 q0,q1,q2'
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[^:]*:11: Error: selected FPU does not support instruction -- `vmax.f16 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vmax.u64 q0,q1,q2'
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[^:]*:13: Error: selected FPU does not support instruction -- `vmax.f32 q0,q1,q2'
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
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[^:]*:18: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
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[^:]*:20: Error: syntax error -- `vmaxeq.s16 q0,q1,q2'
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[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxt.s16 q0,q1,q2'
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[^:]*:23: Error: instruction missing MVE vector predication code -- `vmax.s16 q0,q1,q2'
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[^:]*:25: Error: syntax error -- `vmineq.u32 q0,q1,q2'
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[^:]*:26: Error: syntax error -- `vmineq.u32 q0,q1,q2'
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[^:]*:28: Error: syntax error -- `vmineq.u32 q0,q1,q2'
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[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmint.u32 q0,q1,q2'
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[^:]*:31: Error: instruction missing MVE vector predication code -- `vmin.u32 q0,q1,q2'
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@ -0,0 +1,31 @@
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.macro cond, op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s8 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vmax.s64 q0, q1, q2
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vmax.f16 q0, q1, q2
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vmax.u64 q0, q1, q2
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vmax.f32 q0, q1, q2
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cond vmax
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cond vmin
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it eq
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vmaxeq.s16 q0, q1, q2
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vmaxeq.s16 q0, q1, q2
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vpst
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vmaxeq.s16 q0, q1, q2
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vmaxt.s16 q0, q1, q2
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vpst
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vmax.s16 q0, q1, q2
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it eq
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vmineq.u32 q0, q1, q2
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vmineq.u32 q0, q1, q2
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vpst
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vmineq.u32 q0, q1, q2
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vmint.u32 q0, q1, q2
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vpst
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vmin.u32 q0, q1, q2
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@ -0,0 +1,5 @@
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#name: bad MVE VMAXA and VMINA instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmaxa-vmina-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,29 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmaxa.u8 q0,q1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vmaxa.s64 q0,q1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vmaxa.f16 q0,q1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vmina.u8 q0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vmina.s64 q0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vmina.f16 q0,q1'
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Error: syntax error -- `vmaxaeq.s8 q0,q1'
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[^:]*:20: Error: syntax error -- `vmaxaeq.s8 q0,q1'
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[^:]*:22: Error: syntax error -- `vmaxaeq.s8 q0,q1'
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[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxat.s8 q0,q1'
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[^:]*:25: Error: instruction missing MVE vector predication code -- `vmaxa.s8 q0,q1'
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[^:]*:27: Error: syntax error -- `vminaeq.s8 q0,q1'
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[^:]*:28: Error: syntax error -- `vminaeq.s8 q0,q1'
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[^:]*:30: Error: syntax error -- `vminaeq.s8 q0,q1'
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[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vminat.s8 q0,q1'
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[^:]*:33: Error: instruction missing MVE vector predication code -- `vmina.s8 q0,q1'
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@ -0,0 +1,33 @@
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.macro cond, op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s8 q0, q1
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.endr
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.endm
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.syntax unified
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.thumb
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vmaxa.u8 q0, q1
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vmaxa.s64 q0, q1
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vmaxa.f16 q0, q1
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vmina.u8 q0, q1
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vmina.s64 q0, q1
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vmina.f16 q0, q1
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cond vmaxa
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cond vmina
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it eq
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vmaxaeq.s8 q0, q1
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vmaxaeq.s8 q0, q1
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vpst
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vmaxaeq.s8 q0, q1
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vmaxat.s8 q0, q1
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vpst
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vmaxa.s8 q0, q1
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it eq
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vminaeq.s8 q0, q1
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vminaeq.s8 q0, q1
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vpst
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vminaeq.s8 q0, q1
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vminat.s8 q0, q1
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vpst
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vmina.s8 q0, q1
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@ -0,0 +1,5 @@
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#name: bad MVE VMAXNM and VMINNM instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmaxnm-vminnm-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,27 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnm.f64 q0,q1,q2'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnm.i16 q0,q1,q2'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vminnm.f64 q0,q1,q2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vminnm.i16 q0,q1,q2'
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
|
||||
[^:]*:18: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
|
||||
[^:]*:20: Error: syntax error -- `vmaxnmeq.f32 q0,q1,q2'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmt.f32 q0,q1,q2'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnm.f32 q0,q1,q2'
|
||||
[^:]*:25: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
|
||||
[^:]*:26: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
|
||||
[^:]*:28: Error: syntax error -- `vminnmeq.f32 q0,q1,q2'
|
||||
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmt.f32 q0,q1,q2'
|
||||
[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnm.f32 q0,q1,q2'
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().f16 q0, q1, q2
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vmaxnm.f64 q0, q1, q2
|
||||
vmaxnm.i16 q0, q1, q2
|
||||
vminnm.f64 q0, q1, q2
|
||||
vminnm.i16 q0, q1, q2
|
||||
cond vmaxnm
|
||||
cond vminnm
|
||||
it eq
|
||||
vmaxnmeq.f32 q0, q1, q2
|
||||
vmaxnmeq.f32 q0, q1, q2
|
||||
vpst
|
||||
vmaxnmeq.f32 q0, q1, q2
|
||||
vmaxnmt.f32 q0, q1, q2
|
||||
vpst
|
||||
vmaxnm.f32 q0, q1, q2
|
||||
it eq
|
||||
vminnmeq.f32 q0, q1, q2
|
||||
vminnmeq.f32 q0, q1, q2
|
||||
vpst
|
||||
vminnmeq.f32 q0, q1, q2
|
||||
vminnmt.f32 q0, q1, q2
|
||||
vpst
|
||||
vminnm.f32 q0, q1, q2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VMAXNMA and VMINNMA instructions
|
||||
#as: -march=armv8.1-m.main+mve.fp
|
||||
#error_output: mve-vmaxnma-vminnma-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnma.f64 q0,q1'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnma.i16 q0,q1'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vminnma.f64 q0,q1'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vminnma.i16 q0,q1'
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
|
||||
[^:]*:18: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
|
||||
[^:]*:20: Error: syntax error -- `vmaxnmaeq.f32 q0,q1'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmat.f32 q0,q1'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vmaxnma.f32 q0,q1'
|
||||
[^:]*:25: Error: syntax error -- `vminnmaeq.f32 q0,q1'
|
||||
[^:]*:26: Error: syntax error -- `vminnmaeq.f32 q0,q1'
|
||||
[^:]*:28: Error: syntax error -- `vminnmaeq.f32 q0,q1'
|
||||
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmat.f32 q0,q1'
|
||||
[^:]*:31: Error: instruction missing MVE vector predication code -- `vminnma.f32 q0,q1'
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
.macro cond, op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().f16 q0, q1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vmaxnma.f64 q0, q1
|
||||
vmaxnma.i16 q0, q1
|
||||
vminnma.f64 q0, q1
|
||||
vminnma.i16 q0, q1
|
||||
cond vmaxnma
|
||||
cond vminnma
|
||||
it eq
|
||||
vmaxnmaeq.f32 q0, q1
|
||||
vmaxnmaeq.f32 q0, q1
|
||||
vpst
|
||||
vmaxnmaeq.f32 q0, q1
|
||||
vmaxnmat.f32 q0, q1
|
||||
vpst
|
||||
vmaxnma.f32 q0, q1
|
||||
it eq
|
||||
vminnmaeq.f32 q0, q1
|
||||
vminnmaeq.f32 q0, q1
|
||||
vpst
|
||||
vminnmaeq.f32 q0, q1
|
||||
vminnmat.f32 q0, q1
|
||||
vpst
|
||||
vminnma.f32 q0, q1
|
||||
Loading…
Reference in New Issue