* gas/config/tc-tic4x.c: Fixed proper commandline
parameters. Added support for new opcode-list format. General error message fixups. (c4x_inst_add): Reject insn not for our CPU (md_begin): Added matrix for setting the proper opcode-level & device-flags according to cpu type and revision. Rewrite the opcode hasher. (c4x_operand_parse): Fix opcode bug (c4x_operands_match): New function argument. Added dry-run mechanism, that is optional error generation. Added constraint 'i' and 'j'. (c4x_insn_check): Added new function for post-verification of the generated insn. (md_assemble): Check all opcodes before croaking because of an argument mismatch. Need this to be able to fully support ortogonally arguments. (md_parse_options): Revised commandprompt swicthes and added new ones. (md_show_usage): Complete rewrite of printout. * gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn * gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter * gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter * gas/testsuite/gas/tic4x/allopcodes.S: Add support for new opclass.h changes * gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for the new enhanced opcodes. * gas/testsuite/gas/tic4x/opcodes.s: Regenerate * gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for the enhanced and special insns. * gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite * include/opcode/tic4x.h: File reordering. Added enhanced opcodes. * opcodes/tic4x-dis.c: Added support for enhanced and special insn. (c4x_print_op): Added insn class 'i' and 'j' (c4x_hash_opcode_special): Add to support special insn (c4x_hash_opcode): Update to support the new opcode-list format. Add support for the new special insns. (c4x_disassemble): New opcode-list support.
This commit is contained in:
Svein Seldal
parent
48c5eb8a70
commit
9c87d6c7e4
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@ -22,7 +22,39 @@
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* testsuite/gas/tic4x/tic4x.exp: Create
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* testsuite/gas/tic4x/zeros.d: Create
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* testsuite/gas/tic4x/zeros.s: Create
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* config/tc-tic4x.c: Fixed proper commandline
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parameters. Added support for new opcode-list format. General
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error message fixups.
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(c4x_inst_add): Reject insn not for our CPU
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(md_begin): Added matrix for setting the proper opcode-level &
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device-flags according to cpu type and revision. Rewrite the
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opcode hasher.
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(c4x_operand_parse): Fix opcode bug
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(c4x_operands_match): New function argument. Added dry-run
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mechanism, that is optional error generation. Added constraint 'i'
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and 'j'.
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(c4x_insn_check): Added new function for post-verification of the
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generated insn.
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(md_assemble): Check all opcodes before croaking because of an
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argument mismatch. Need this to be able to fully support
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ortogonally arguments.
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(md_parse_options): Revised commandprompt swicthes and added new
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ones.
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(md_show_usage): Complete rewrite of printout.
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* testsuite/gas/tic4x/addressing.s: Fix bug in one insn
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* testsuite/gas/tic4x/addressing_c3x.d: Update thereafter
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* testsuite/gas/tic4x/addressing_c4x.d: Update thereafter
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* testsuite/gas/tic4x/allopcodes.S: Add support for new
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opclass.h changes
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* testsuite/gas/tic4x/opclasses.h: Added testsuites for
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the new enhanced opcodes.
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* testsuite/gas/tic4x/opcodes.s: Regenerate
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* testsuite/gas/tic4x/opcodes_c3x.d: Update from above
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* testsuite/gas/tic4x/opcodes_c4x.d: Update from above
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* testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for
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the enhanced and special insns.
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* testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite
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2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com>
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* config/tc-tic4x.c: Remove c4x_pseudo_ignore function.
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@ -42,22 +42,7 @@
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o Evaluation of constant floating point expressions (expr.c needs
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work!)
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o Warnings issued if parallel load of same register. Applies to LL
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class. Can be applied to destination of the LS class as well, but
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the test will be more complex.
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o Support 'abc' constants?
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o Support new opcodes and implement a silicon version switch (maybe
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-mpg)
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o Disallow non-float registers in float instructions.
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o Make sure the source and destination register is NOT equal when
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the C4X LDA insn is used (arg mode Q,Y)
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o Merge the C3x op-table and the c4x op-table, and adhere to the
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last argument when parsing the hash.
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o Support 'abc' constants (that is 0x616263)
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*/
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#include <stdio.h>
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@ -88,8 +73,42 @@ static struct hash_control *c4x_op_hash = NULL;
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static struct hash_control *c4x_asg_hash = NULL;
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static unsigned int c4x_cpu = 0; /* Default to TMS320C40. */
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static unsigned int c4x_revision = 0; /* CPU revision */
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static unsigned int c4x_idle2 = 0; /* Idle2 support */
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static unsigned int c4x_lowpower = 0; /* Lowpower support */
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static unsigned int c4x_enhanced = 0; /* Enhanced opcode support */
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static unsigned int c4x_big_model = 0; /* Default to small memory model. */
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static unsigned int c4x_reg_args = 0; /* Default to args passed on stack. */
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static unsigned long c4x_oplevel = 0; /* Opcode level */
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#define OPTION_CPU 'm'
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#define OPTION_BIG (OPTION_MD_BASE + 1)
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#define OPTION_SMALL (OPTION_MD_BASE + 2)
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#define OPTION_MEMPARM (OPTION_MD_BASE + 3)
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#define OPTION_REGPARM (OPTION_MD_BASE + 4)
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#define OPTION_IDLE2 (OPTION_MD_BASE + 5)
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#define OPTION_LOWPOWER (OPTION_MD_BASE + 6)
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#define OPTION_ENHANCED (OPTION_MD_BASE + 7)
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#define OPTION_REV (OPTION_MD_BASE + 8)
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CONST char *md_shortopts = "bm:prs";
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struct option md_longopts[] =
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{
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{ "mcpu", required_argument, NULL, OPTION_CPU },
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{ "mdsp", required_argument, NULL, OPTION_CPU },
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{ "mbig", no_argument, NULL, OPTION_BIG },
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{ "msmall", no_argument, NULL, OPTION_SMALL },
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{ "mmemparm", no_argument, NULL, OPTION_MEMPARM },
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{ "mregparm", no_argument, NULL, OPTION_REGPARM },
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{ "midle2", no_argument, NULL, OPTION_IDLE2 },
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{ "mlowpower", no_argument, NULL, OPTION_LOWPOWER },
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{ "menhanced", no_argument, NULL, OPTION_ENHANCED },
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{ "mrev", required_argument, NULL, OPTION_REV },
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{ NULL, no_argument, NULL, 0 }
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};
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size_t md_longopts_size = sizeof (md_longopts);
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typedef enum
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{
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@ -185,7 +204,9 @@ static int c4x_indirect_parse
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static char *c4x_operand_parse
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PARAMS ((char *, c4x_operand_t *));
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static int c4x_operands_match
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PARAMS ((c4x_inst_t *, c4x_insn_t *));
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PARAMS ((c4x_inst_t *, c4x_insn_t *, int));
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static void c4x_insn_check
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PARAMS ((c4x_insn_t *));
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static void c4x_insn_output
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PARAMS ((c4x_insn_t *));
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static int c4x_operands_parse
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@ -1239,11 +1260,11 @@ c4x_version (x)
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input_line_pointer =
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c4x_expression_abs (input_line_pointer, &temp);
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if (!IS_CPU_C3X (temp) && !IS_CPU_C4X (temp))
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as_bad ("This assembler does not support processor generation %d\n",
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as_bad ("This assembler does not support processor generation %d",
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temp);
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if (c4x_cpu && temp != c4x_cpu)
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as_warn ("Changing processor generation on fly not supported...\n");
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as_warn ("Changing processor generation on fly not supported...");
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c4x_cpu = temp;
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demand_empty_rest_of_line ();
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}
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@ -1389,6 +1410,11 @@ c4x_inst_add (insts)
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d = name;
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/* We do not care about INSNs that is not a part of our
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oplevel setting */
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if (!insts->oplevel & c4x_oplevel)
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return ok;
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while (1)
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{
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switch (*s)
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@ -1450,6 +1476,34 @@ md_begin ()
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int ok = 1;
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unsigned int i;
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/* Setup the proper opcode level according to the
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commandline parameters */
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c4x_oplevel = OP_C3X;
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if ( IS_CPU_C4X(c4x_cpu) )
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c4x_oplevel |= OP_C4X;
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if ( ( c4x_cpu == 31 && c4x_revision >= 6)
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|| (c4x_cpu == 32 && c4x_revision >= 2)
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|| (c4x_cpu == 33)
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|| c4x_enhanced )
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c4x_oplevel |= OP_ENH;
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if ( ( c4x_cpu == 30 && c4x_revision >= 7)
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|| (c4x_cpu == 31 && c4x_revision >= 5)
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|| (c4x_cpu == 32)
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|| c4x_lowpower )
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c4x_oplevel |= OP_LPWR;
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if ( ( c4x_cpu == 30 && c4x_revision >= 7)
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|| (c4x_cpu == 31 && c4x_revision >= 5)
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|| (c4x_cpu == 32)
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|| (c4x_cpu == 33)
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|| (c4x_cpu == 40 && c4x_revision >= 5)
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|| (c4x_cpu == 44)
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|| c4x_idle2 )
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c4x_oplevel |= OP_IDLE2;
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/* Create hash table for mnemonics. */
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c4x_op_hash = hash_new ();
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@ -1457,14 +1511,8 @@ md_begin ()
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c4x_asg_hash = hash_new ();
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/* Add mnemonics to hash table, expanding conditional mnemonics on fly. */
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for (i = 0; i < c3x_num_insts; i++)
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ok &= c4x_inst_add ((void *) &c3x_insts[i]);
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if (IS_CPU_C4X (c4x_cpu))
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{
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for (i = 0; i < c4x_num_insts; i++)
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ok &= c4x_inst_add ((void *) &c4x_insts[i]);
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}
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for (i = 0; i < c4x_num_insts; i++)
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ok &= c4x_inst_add ((void *) &c4x_insts[i]);
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/* Create dummy inst to avoid errors accessing end of table. */
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c4x_inst_make ("", 0, "");
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@ -1695,12 +1743,12 @@ c4x_operand_parse (s, operand)
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case '*':
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ret = -1;
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for (i = 0; i < num_indirects; i++)
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for (i = 0; i < c4x_num_indirects; i++)
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if ((ret = c4x_indirect_parse (operand, &c4x_indirects[i])))
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break;
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if (ret < 0)
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break;
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if (i < num_indirects)
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if (i < c4x_num_indirects)
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{
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operand->mode = M_INDIRECT;
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/* Indirect addressing mode number. */
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@ -1753,9 +1801,10 @@ c4x_operand_parse (s, operand)
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}
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static int
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c4x_operands_match (inst, insn)
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c4x_operands_match (inst, insn, check)
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c4x_inst_t *inst;
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c4x_insn_t *insn;
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int check;
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{
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const char *args = inst->args;
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unsigned long opcode = inst->opcode;
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@ -1809,8 +1858,9 @@ c4x_operands_match (inst, insn)
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}
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else
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{
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as_bad ("LDF's immediate value of %ld is too large",
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(long) exp->X_add_number);
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if (!check)
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as_bad ("Immediate value of %ld is too large for ldf",
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(long) exp->X_add_number);
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ret = -1;
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continue;
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}
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@ -1836,8 +1886,9 @@ c4x_operands_match (inst, insn)
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}
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else
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{
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as_bad ("Direct value of %ld is too large",
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(long) exp->X_add_number);
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if (!check)
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as_bad ("Direct value of %ld is too large",
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(long) exp->X_add_number);
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ret = -1;
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continue;
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}
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@ -1858,7 +1909,8 @@ c4x_operands_match (inst, insn)
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INSERTU (opcode, reg - REG_AR0, 24, 22);
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else
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{
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as_bad ("Destination register must be ARn");
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if (!check)
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as_bad ("Destination register must be ARn");
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ret = -1;
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}
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continue;
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@ -1876,8 +1928,9 @@ c4x_operands_match (inst, insn)
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}
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else
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{
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as_bad ("Immediate value of %ld is too large",
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(long) exp->X_add_number);
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if (!check)
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as_bad ("Immediate value of %ld is too large",
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(long) exp->X_add_number);
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ret = -1;
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continue;
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}
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@ -1904,8 +1957,9 @@ c4x_operands_match (inst, insn)
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if (operand->expr.X_add_number != 0
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&& operand->expr.X_add_number != 0x18)
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{
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as_bad ("Invalid indirect addressing mode");
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ret = -1;
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if (!check)
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as_bad ("Invalid indirect addressing mode");
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ret = -1;
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continue;
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}
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INSERTU (opcode, operand->aregno - REG_AR0, 2, 0);
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@ -1927,7 +1981,8 @@ c4x_operands_match (inst, insn)
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INSERTU (opcode, reg, 7, 0);
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else
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{
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as_bad ("Register must be Rn");
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if (!check)
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as_bad ("Register must be Rn");
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ret = -1;
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}
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continue;
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@ -1966,7 +2021,8 @@ c4x_operands_match (inst, insn)
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INSERTU (opcode, reg, 15, 8);
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else
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{
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as_bad ("Register must be Rn");
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if (!check)
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as_bad ("Register must be Rn");
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ret = -1;
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}
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continue;
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@ -1979,11 +2035,23 @@ c4x_operands_match (inst, insn)
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INSERTU (opcode, reg - REG_R0, 18, 16);
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else
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{
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as_bad ("Register must be R0--R7");
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if (!check)
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as_bad ("Register must be R0--R7");
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ret = -1;
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}
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continue;
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case 'i':
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if ( operand->mode == M_REGISTER
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&& c4x_oplevel & OP_ENH )
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{
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reg = exp->X_add_number;
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INSERTU (opcode, reg, 4, 0);
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INSERTU (opcode, 7, 7, 5);
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continue;
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}
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/* Fallthrough */
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case 'I':
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if (operand->mode != M_INDIRECT)
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break;
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|
@ -1991,8 +2059,9 @@ c4x_operands_match (inst, insn)
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{
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if (IS_CPU_C4X (c4x_cpu))
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break;
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as_bad ("Invalid indirect addressing mode displacement %d",
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operand->disp);
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if (!check)
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as_bad ("Invalid indirect addressing mode displacement %d",
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operand->disp);
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ret = -1;
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continue;
|
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}
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|
|
@ -2000,6 +2069,17 @@ c4x_operands_match (inst, insn)
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INSERTU (opcode, operand->expr.X_add_number, 7, 3);
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continue;
|
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|
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case 'j':
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if ( operand->mode == M_REGISTER
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&& c4x_oplevel & OP_ENH )
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{
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reg = exp->X_add_number;
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INSERTU (opcode, reg, 12, 8);
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INSERTU (opcode, 7, 15, 13);
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||||
continue;
|
||||
}
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/* Fallthrough */
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case 'J':
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if (operand->mode != M_INDIRECT)
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break;
|
||||
|
|
@ -2007,8 +2087,9 @@ c4x_operands_match (inst, insn)
|
|||
{
|
||||
if (IS_CPU_C4X (c4x_cpu))
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break;
|
||||
as_bad ("Invalid indirect addressing mode displacement %d",
|
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operand->disp);
|
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if (!check)
|
||||
as_bad ("Invalid indirect addressing mode displacement %d",
|
||||
operand->disp);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2024,7 +2105,8 @@ c4x_operands_match (inst, insn)
|
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INSERTU (opcode, reg - REG_R0, 21, 19);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be R0--R7");
|
||||
if (!check)
|
||||
as_bad ("Register must be R0--R7");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2037,7 +2119,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg - REG_R0, 24, 22);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be R0--R7");
|
||||
if (!check)
|
||||
as_bad ("Register must be R0--R7");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2050,7 +2133,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg - REG_R2, 22, 22);
|
||||
else
|
||||
{
|
||||
as_bad ("Destination register must be R2 or R3");
|
||||
if (!check)
|
||||
as_bad ("Destination register must be R2 or R3");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2063,7 +2147,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg - REG_R0, 23, 23);
|
||||
else
|
||||
{
|
||||
as_bad ("Destination register must be R0 or R1");
|
||||
if (!check)
|
||||
as_bad ("Destination register must be R0 or R1");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2077,7 +2162,8 @@ c4x_operands_match (inst, insn)
|
|||
if (operand->expr.X_add_number != 0
|
||||
&& operand->expr.X_add_number != 0x18)
|
||||
{
|
||||
as_bad ("Invalid indirect addressing mode");
|
||||
if (!check)
|
||||
as_bad ("Invalid indirect addressing mode");
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2098,8 +2184,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Displacement value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Displacement value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2125,7 +2212,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg, 15, 0);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be Rn");
|
||||
if (!check)
|
||||
as_bad ("Register must be Rn");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2146,7 +2234,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg, 20, 16);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be Rn");
|
||||
if (!check)
|
||||
as_bad ("Register must be Rn");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2156,7 +2245,8 @@ c4x_operands_match (inst, insn)
|
|||
break;
|
||||
if (exp->X_op == O_big)
|
||||
{
|
||||
as_bad ("Floating point number not valid in expression");
|
||||
if (!check)
|
||||
as_bad ("Floating point number not valid in expression");
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2169,8 +2259,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Signed immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Signed immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2210,8 +2301,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Immediate value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Immediate value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2230,8 +2322,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Unsigned immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Unsigned immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2267,8 +2360,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Immediate value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Immediate value of %ld is too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2282,7 +2376,8 @@ c4x_operands_match (inst, insn)
|
|||
break;
|
||||
if (exp->X_op == O_big)
|
||||
{
|
||||
as_bad ("Floating point number not valid in expression");
|
||||
if (!check)
|
||||
as_bad ("Floating point number not valid in expression");
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2295,8 +2390,9 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
else
|
||||
{
|
||||
as_bad ("Immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
if (!check)
|
||||
as_bad ("Immediate value %ld too large",
|
||||
(long) exp->X_add_number);
|
||||
ret = -1;
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2313,7 +2409,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg - REG_IVTP, 4, 0);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be ivtp or tvtp");
|
||||
if (!check)
|
||||
as_bad ("Register must be ivtp or tvtp");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2326,7 +2423,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg, 20, 16);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be address register");
|
||||
if (!check)
|
||||
as_bad ("Register must be address register");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2339,7 +2437,8 @@ c4x_operands_match (inst, insn)
|
|||
INSERTU (opcode, reg - REG_IVTP, 20, 16);
|
||||
else
|
||||
{
|
||||
as_bad ("Register must be ivtp or tvtp");
|
||||
if (!check)
|
||||
as_bad ("Register must be ivtp or tvtp");
|
||||
ret = -1;
|
||||
}
|
||||
continue;
|
||||
|
|
@ -2386,6 +2485,38 @@ c4x_operands_match (inst, insn)
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
c4x_insn_check (insn)
|
||||
c4x_insn_t *insn;
|
||||
{
|
||||
|
||||
if (!strcmp(insn->name, "lda"))
|
||||
{
|
||||
if (insn->num_operands < 2 || insn->num_operands > 2)
|
||||
as_fatal ("Illegal internal LDA insn definition");
|
||||
|
||||
if ( insn->operands[0].mode == M_REGISTER
|
||||
&& insn->operands[1].mode == M_REGISTER
|
||||
&& insn->operands[0].expr.X_add_number == insn->operands[1].expr.X_add_number )
|
||||
as_bad ("Source and destination register should not be equal");
|
||||
}
|
||||
else if( !strcmp(insn->name, "ldi_ldi")
|
||||
|| !strcmp(insn->name, "ldi1_ldi2")
|
||||
|| !strcmp(insn->name, "ldi2_ldi1")
|
||||
|| !strcmp(insn->name, "ldf_ldf")
|
||||
|| !strcmp(insn->name, "ldf1_ldf2")
|
||||
|| !strcmp(insn->name, "ldf2_ldf1") )
|
||||
{
|
||||
if ( insn->num_operands < 4 && insn->num_operands > 5 )
|
||||
as_fatal ("Illegal internal %s insn definition", insn->name);
|
||||
|
||||
if ( insn->operands[1].mode == M_REGISTER
|
||||
&& insn->operands[insn->num_operands-1].mode == M_REGISTER
|
||||
&& insn->operands[1].expr.X_add_number == insn->operands[insn->num_operands-1].expr.X_add_number )
|
||||
as_warn ("Equal parallell destination registers, one result will be discarded");
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
c4x_insn_output (insn)
|
||||
c4x_insn_t *insn;
|
||||
|
|
@ -2445,6 +2576,7 @@ md_assemble (str)
|
|||
int i;
|
||||
int parsed = 0;
|
||||
c4x_inst_t *inst; /* Instruction template. */
|
||||
c4x_inst_t *first_inst;
|
||||
|
||||
if (str && insn->parallel)
|
||||
{
|
||||
|
|
@ -2491,23 +2623,30 @@ md_assemble (str)
|
|||
return;
|
||||
}
|
||||
|
||||
/* FIXME: The list of templates should be scanned
|
||||
for the candidates with the desired number of operands.
|
||||
We shouldn't issue error messages until we have
|
||||
whittled the list of candidate templates to the most
|
||||
likely one... We could cache a parsed form of the templates
|
||||
to reduce the time required to match a template. */
|
||||
|
||||
inst = insn->inst;
|
||||
|
||||
first_inst = NULL;
|
||||
do
|
||||
ok = c4x_operands_match (inst, insn);
|
||||
while (!ok && !strcmp (inst->name, inst[1].name) && inst++);
|
||||
{
|
||||
ok = c4x_operands_match (inst, insn, 1);
|
||||
if (ok < 0)
|
||||
{
|
||||
if (!first_inst)
|
||||
first_inst = inst;
|
||||
ok = 0;
|
||||
}
|
||||
} while (!ok && !strcmp (inst->name, inst[1].name) && inst++);
|
||||
|
||||
if (ok > 0)
|
||||
c4x_insn_output (insn);
|
||||
{
|
||||
c4x_insn_check (insn);
|
||||
c4x_insn_output (insn);
|
||||
}
|
||||
else if (!ok)
|
||||
as_bad ("Invalid operands for %s", insn->name);
|
||||
{
|
||||
if (first_inst)
|
||||
c4x_operands_match (first_inst, insn, 0);
|
||||
as_bad ("Invalid operands for %s", insn->name);
|
||||
}
|
||||
else
|
||||
as_bad ("Invalid instruction %s", insn->name);
|
||||
}
|
||||
|
|
@ -2715,13 +2854,6 @@ md_estimate_size_before_relax (fragP, segtype)
|
|||
return 0;
|
||||
}
|
||||
|
||||
CONST char *md_shortopts = "bm:prs";
|
||||
struct option md_longopts[] =
|
||||
{
|
||||
{NULL, no_argument, NULL, 0}
|
||||
};
|
||||
|
||||
size_t md_longopts_size = sizeof (md_longopts);
|
||||
|
||||
int
|
||||
md_parse_option (c, arg)
|
||||
|
|
@ -2730,25 +2862,54 @@ md_parse_option (c, arg)
|
|||
{
|
||||
switch (c)
|
||||
{
|
||||
case 'b': /* big model */
|
||||
c4x_big_model = 1;
|
||||
break;
|
||||
case 'm': /* -m[c][34]x */
|
||||
case OPTION_CPU: /* cpu brand */
|
||||
if (tolower (*arg) == 'c')
|
||||
arg++;
|
||||
c4x_cpu = atoi (arg);
|
||||
if (!IS_CPU_C3X (c4x_cpu) && !IS_CPU_C4X (c4x_cpu))
|
||||
as_warn ("Unsupported processor generation %d\n", c4x_cpu);
|
||||
as_warn ("Unsupported processor generation %d", c4x_cpu);
|
||||
break;
|
||||
case 'p': /* push args */
|
||||
|
||||
case OPTION_REV: /* cpu revision */
|
||||
c4x_revision = atoi (arg);
|
||||
break;
|
||||
|
||||
case 'b':
|
||||
as_warn ("Option -b is depreciated, please use -mbig");
|
||||
case OPTION_BIG: /* big model */
|
||||
c4x_big_model = 1;
|
||||
break;
|
||||
|
||||
case 'p':
|
||||
as_warn ("Option -p is depreciated, please use -mmemparm");
|
||||
case OPTION_MEMPARM: /* push args */
|
||||
c4x_reg_args = 0;
|
||||
break;
|
||||
case 'r': /* register args */
|
||||
|
||||
case 'r':
|
||||
as_warn ("Option -r is depreciated, please use -mregparm");
|
||||
case OPTION_REGPARM: /* register args */
|
||||
c4x_reg_args = 1;
|
||||
break;
|
||||
case 's': /* small model */
|
||||
|
||||
case 's':
|
||||
as_warn ("Option -s is depreciated, please use -msmall");
|
||||
case OPTION_SMALL: /* small model */
|
||||
c4x_big_model = 0;
|
||||
break;
|
||||
|
||||
case OPTION_IDLE2:
|
||||
c4x_idle2 = 1;
|
||||
break;
|
||||
|
||||
case OPTION_LOWPOWER:
|
||||
c4x_lowpower = 1;
|
||||
break;
|
||||
|
||||
case OPTION_ENHANCED:
|
||||
c4x_enhanced = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2760,15 +2921,26 @@ void
|
|||
md_show_usage (stream)
|
||||
FILE *stream;
|
||||
{
|
||||
fputs ("\
|
||||
C[34]x options:\n\
|
||||
-m30 | -m31 | -m32 | -m33 | -m40 | -m44\n\
|
||||
specify variant of architecture\n\
|
||||
-b big memory model\n\
|
||||
-p pass arguments on stack\n\
|
||||
-r pass arguments in registers (default)\n\
|
||||
-s small memory model (default)\n",
|
||||
stream);
|
||||
fprintf (stream,
|
||||
_("\nTIC4X options:\n"
|
||||
" -mcpu=CPU -mCPU select architecture variant. CPU can be:\n"
|
||||
" 30 - TMS320C30\n"
|
||||
" 31 - TMS320C31, TMS320LC31\n"
|
||||
" 32 - TMS320C32\n"
|
||||
" 33 - TMS320VC33\n"
|
||||
" 40 - TMS320C40\n"
|
||||
" 44 - TMS320C44\n"
|
||||
" -mrev=REV set cpu hardware revision (integer numbers).\n"
|
||||
" Combinations of -mcpu and -mrev will enable/disable\n"
|
||||
" the appropriate options (-midle2, -mlowpower and\n"
|
||||
" -menhanced) according to the selected type\n"
|
||||
" -mbig select big memory model\n"
|
||||
" -msmall select small memory model (default)\n"
|
||||
" -mregparm select register parameters (default)\n"
|
||||
" -mmemparm select memory parameters\n"
|
||||
" -midle2 enable IDLE2 support\n"
|
||||
" -mlowpower enable LOPOWER and MAXSPEED support\n"
|
||||
" -menhanced enable enhanced opcode support\n"));
|
||||
}
|
||||
|
||||
/* This is called when a line is unrecognized. This is used to handle
|
||||
|
|
@ -3010,7 +3182,7 @@ tc_gen_reloc (seg, fixP)
|
|||
if (reloc->howto == (reloc_howto_type *) NULL)
|
||||
{
|
||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||
"reloc %d not supported by object file format",
|
||||
"Reloc %d not supported by object file format",
|
||||
(int) fixP->fx_r_type);
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -231,7 +231,7 @@ Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
|
|||
;;
|
||||
;; Type K - Register (0-7)
|
||||
;;
|
||||
Type_K: ldf *AR0,R0 &|| ldf *AR0,R0
|
||||
Type_K: ldf *AR0,R0 &|| ldf *AR0,R1
|
||||
ldf *AR0,R0 &|| ldf *AR0,R2
|
||||
ldf *AR0,R0 &|| ldf *AR0,R7
|
||||
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ Disassembly of section .text:
|
|||
92: 20a02000.*
|
||||
|
||||
00000093 <Type_K>:
|
||||
93: c400c0c0.*
|
||||
93: c408c0c0.*
|
||||
94: c410c0c0.*
|
||||
95: c438c0c0.*
|
||||
|
||||
|
|
|
|||
|
|
@ -190,7 +190,7 @@ Disassembly of section .text:
|
|||
95: 20a02000.*
|
||||
|
||||
00000096 <Type_K>:
|
||||
96: c400c0c0.*
|
||||
96: c408c0c0.*
|
||||
97: c410c0c0.*
|
||||
98: c438c0c0.*
|
||||
|
||||
|
|
|
|||
|
|
@ -6,201 +6,236 @@
|
|||
;;;
|
||||
;;; To rebuild this file you must use
|
||||
;;; ./rebuild.sh
|
||||
;;;
|
||||
;;; These definitions are used within this file:
|
||||
;;; TEST_C3X Enables testing of c3x opcodes
|
||||
;;; TEST_C4X Enables testing of c4x opcodes
|
||||
;;; TEST_ENH Enable testing of enhanced opcodes
|
||||
;;; TEST_IDLE2 Enable testing of IDLE2 command
|
||||
;;; TEST_LPWR Enable testing of LOPOWER commands
|
||||
;;;
|
||||
#include "opclasses.h"
|
||||
|
||||
.text
|
||||
start: B_CLASS( absf )
|
||||
P_CLASS( absf, stf )
|
||||
A_CLASS( absi )
|
||||
P_CLASS( absi, sti )
|
||||
A_CLASS( addc )
|
||||
TC_CLASS( addc )
|
||||
B_CLASS( addf )
|
||||
SC_CLASS( addf )
|
||||
QC_CLASS( addf, stf )
|
||||
A_CLASS( addi )
|
||||
TC_CLASS( addi )
|
||||
QC_CLASS( addi, sti )
|
||||
AU_CLASS( and )
|
||||
TC_CLASS( and )
|
||||
QC_CLASS( and, sti )
|
||||
AU_CLASS( andn )
|
||||
T_CLASS( andn )
|
||||
A_CLASS( ash )
|
||||
T_CLASS( ash )
|
||||
Q_CLASS( ash, sti )
|
||||
J_CLASS( bC, b )
|
||||
J_CLASS( bCd, bd )
|
||||
;;------------------------------------
|
||||
;; C3X INSNS
|
||||
;;------------------------------------
|
||||
start: B_CLASS( absf, TEST_C3X )
|
||||
P_CLASS( absf, stf, TEST_C3X )
|
||||
A_CLASS( absi, TEST_C3X )
|
||||
P_CLASS( absi, sti, TEST_C3X )
|
||||
A_CLASS( addc, TEST_C3X )
|
||||
TC_CLASS( addc, TEST_C3X )
|
||||
B_CLASS( addf, TEST_C3X )
|
||||
SC_CLASS( addf, TEST_C3X )
|
||||
QC_CLASS( addf, stf, TEST_C3X )
|
||||
A_CLASS( addi, TEST_C3X )
|
||||
TC_CLASS( addi, TEST_C3X )
|
||||
QC_CLASS( addi, sti, TEST_C3X )
|
||||
AU_CLASS( and, TEST_C3X )
|
||||
TC_CLASS( and, TEST_C3X )
|
||||
QC_CLASS( and, sti, TEST_C3X )
|
||||
AU_CLASS( andn, TEST_C3X )
|
||||
T_CLASS( andn, TEST_C3X )
|
||||
A_CLASS( ash, TEST_C3X )
|
||||
T_CLASS( ash, TEST_C3X )
|
||||
Q_CLASS( ash, sti, TEST_C3X )
|
||||
J_CLASS( bC, b, TEST_C3X )
|
||||
J_CLASS( bCd, bd, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
br_I: br start
|
||||
brd_I: brd start
|
||||
call_I: call start
|
||||
call_JS: callc R0
|
||||
callc start
|
||||
B_CLASS( cmpf )
|
||||
S2_CLASS( cmpf )
|
||||
A_CLASS( cmpi )
|
||||
T2_CLASS( cmpi )
|
||||
D_CLASS( dbC, db )
|
||||
D_CLASS( dbCd, dbd )
|
||||
AF_CLASS( fix )
|
||||
P_CLASS( fix, sti )
|
||||
BI_CLASS( float )
|
||||
P_CLASS( float, stf )
|
||||
.endif
|
||||
B_CLASS( cmpf, TEST_C3X )
|
||||
S2_CLASS( cmpf, TEST_C3X )
|
||||
A_CLASS( cmpi, TEST_C3X )
|
||||
T2_CLASS( cmpi, TEST_C3X )
|
||||
D_CLASS( dbC, db, TEST_C3X )
|
||||
D_CLASS( dbCd, dbd, TEST_C3X )
|
||||
AF_CLASS( fix, TEST_C3X )
|
||||
P_CLASS( fix, sti, TEST_C3X )
|
||||
BI_CLASS( float, TEST_C3X )
|
||||
P_CLASS( float, stf, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
iack_Z: iack @start
|
||||
iack *+AR0(1)
|
||||
idle_Z: idle
|
||||
.endif
|
||||
.ifdef TEST_IDLE2
|
||||
idle2_Z: idle2
|
||||
.endif
|
||||
B_CLASS( lde )
|
||||
B_CLASS( ldf )
|
||||
LL_CLASS( ldf )
|
||||
P_CLASS( ldf, stf )
|
||||
BB_CLASS( ldfC )
|
||||
B6_CLASS( ldfi )
|
||||
A_CLASS( ldi )
|
||||
LL_CLASS( ldi )
|
||||
P_CLASS( ldi, sti )
|
||||
AB_CLASS( ldiC )
|
||||
A6_CLASS( ldii )
|
||||
B_CLASS( lde, TEST_C3X )
|
||||
B_CLASS( ldf, TEST_C3X )
|
||||
LL_CLASS( ldf, TEST_C3X )
|
||||
P_CLASS( ldf, stf, TEST_C3X )
|
||||
BB_CLASS( ldfC, TEST_C3X )
|
||||
B6_CLASS( ldfi, TEST_C3X )
|
||||
A_CLASS( ldi, TEST_C3X )
|
||||
LL_CLASS( ldi, TEST_C3X )
|
||||
P_CLASS( ldi, sti, TEST_C3X )
|
||||
AB_CLASS( ldiC, TEST_C3X )
|
||||
A6_CLASS( ldii, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
ldp_Z: ldp start
|
||||
B_CLASS( ldm )
|
||||
.endif
|
||||
B_CLASS( ldm, TEST_C3X )
|
||||
.ifdef TEST_LPWR
|
||||
lopower_Z: lopower
|
||||
.endif
|
||||
A_CLASS( lsh )
|
||||
T_CLASS( lsh )
|
||||
Q_CLASS( lsh, sti )
|
||||
A_CLASS( lsh, TEST_C3X )
|
||||
T_CLASS( lsh, TEST_C3X )
|
||||
Q_CLASS( lsh, sti, TEST_C3X )
|
||||
.ifdef TEST_LPWR
|
||||
maxspeed_Z: maxspeed
|
||||
.endif
|
||||
B_CLASS( mpyf )
|
||||
SC_CLASS( mpyf )
|
||||
M_CLASS( mpyf, addf )
|
||||
QC_CLASS( mpyf, stf )
|
||||
M_CLASS( mpyf, subf )
|
||||
A_CLASS( mpyi )
|
||||
TC_CLASS( mpyi )
|
||||
M_CLASS( mpyi, addi )
|
||||
QC_CLASS( mpyi, sti )
|
||||
M_CLASS( mpyi, subi )
|
||||
A_CLASS( negb )
|
||||
B_CLASS( negf )
|
||||
P_CLASS( negf, stf )
|
||||
A_CLASS( negi )
|
||||
P_CLASS( negi, sti )
|
||||
A2_CLASS( nop )
|
||||
B_CLASS( norm )
|
||||
AU_CLASS( not )
|
||||
P_CLASS( not, sti )
|
||||
AU_CLASS( or )
|
||||
TC_CLASS( or )
|
||||
QC_CLASS( or, sti )
|
||||
R_CLASS( pop )
|
||||
RF_CLASS( popf )
|
||||
R_CLASS( push )
|
||||
RF_CLASS( pushf )
|
||||
B_CLASS( mpyf, TEST_C3X )
|
||||
SC_CLASS( mpyf, TEST_C3X )
|
||||
M_CLASS( mpyf, addf, TEST_C3X )
|
||||
QC_CLASS( mpyf, stf, TEST_C3X )
|
||||
M_CLASS( mpyf, subf, TEST_C3X )
|
||||
A_CLASS( mpyi, TEST_C3X )
|
||||
TC_CLASS( mpyi, TEST_C3X )
|
||||
M_CLASS( mpyi, addi, TEST_C3X )
|
||||
QC_CLASS( mpyi, sti, TEST_C3X )
|
||||
M_CLASS( mpyi, subi, TEST_C3X )
|
||||
A_CLASS( negb, TEST_C3X )
|
||||
B_CLASS( negf, TEST_C3X )
|
||||
P_CLASS( negf, stf, TEST_C3X )
|
||||
A_CLASS( negi, TEST_C3X )
|
||||
P_CLASS( negi, sti, TEST_C3X )
|
||||
A2_CLASS( nop, TEST_C3X )
|
||||
B_CLASS( norm, TEST_C3X )
|
||||
AU_CLASS( not, TEST_C3X )
|
||||
P_CLASS( not, sti, TEST_C3X )
|
||||
AU_CLASS( or, TEST_C3X )
|
||||
TC_CLASS( or, TEST_C3X )
|
||||
QC_CLASS( or, sti, TEST_C3X )
|
||||
R_CLASS( pop, TEST_C3X )
|
||||
RF_CLASS( popf, TEST_C3X )
|
||||
R_CLASS( push, TEST_C3X )
|
||||
RF_CLASS( pushf, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
reti_Z: retiC
|
||||
reti
|
||||
rets_Z: retsC
|
||||
rets
|
||||
B_CLASS( rnd )
|
||||
R_CLASS( rol )
|
||||
R_CLASS( rolc )
|
||||
R_CLASS( ror )
|
||||
R_CLASS( rorc )
|
||||
.endif
|
||||
B_CLASS( rnd, TEST_C3X )
|
||||
R_CLASS( rol, TEST_C3X )
|
||||
R_CLASS( rolc, TEST_C3X )
|
||||
R_CLASS( ror, TEST_C3X )
|
||||
R_CLASS( rorc, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
rptb_I2: rptb start
|
||||
A3_CLASS( rpts )
|
||||
.endif
|
||||
A3_CLASS( rpts, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
sigi_Z: sigi
|
||||
B7_CLASS( stf )
|
||||
LS_CLASS( stf )
|
||||
B7_CLASS( stfi )
|
||||
A7_CLASS( sti )
|
||||
LS_CLASS( sti )
|
||||
A7_CLASS( stii )
|
||||
A_CLASS( subb )
|
||||
T_CLASS( subb )
|
||||
A_CLASS( subc )
|
||||
B_CLASS( subf )
|
||||
S_CLASS( subf )
|
||||
Q_CLASS( subf, stf )
|
||||
A_CLASS( subi )
|
||||
T_CLASS( subi )
|
||||
Q_CLASS( subi, sti )
|
||||
A_CLASS( subrb )
|
||||
B_CLASS( subrf )
|
||||
A_CLASS( subri )
|
||||
.endif
|
||||
B7_CLASS( stf, TEST_C3X )
|
||||
LS_CLASS( stf, TEST_C3X )
|
||||
B7_CLASS( stfi, TEST_C3X )
|
||||
A7_CLASS( sti, TEST_C3X )
|
||||
LS_CLASS( sti, TEST_C3X )
|
||||
A7_CLASS( stii, TEST_C3X )
|
||||
A_CLASS( subb, TEST_C3X )
|
||||
T_CLASS( subb, TEST_C3X )
|
||||
A_CLASS( subc, TEST_C3X )
|
||||
B_CLASS( subf, TEST_C3X )
|
||||
S_CLASS( subf, TEST_C3X )
|
||||
Q_CLASS( subf, stf, TEST_C3X )
|
||||
A_CLASS( subi, TEST_C3X )
|
||||
T_CLASS( subi, TEST_C3X )
|
||||
Q_CLASS( subi, sti, TEST_C3X )
|
||||
A_CLASS( subrb, TEST_C3X )
|
||||
B_CLASS( subrf, TEST_C3X )
|
||||
A_CLASS( subri, TEST_C3X )
|
||||
.ifdef TEST_C3X
|
||||
swi_Z: swi
|
||||
trap_Z: trapC 10
|
||||
trap 10
|
||||
AU_CLASS( tstb )
|
||||
T2C_CLASS( tstb )
|
||||
AU_CLASS( xor )
|
||||
TC_CLASS( xor )
|
||||
QC_CLASS( xor, sti )
|
||||
|
||||
.endif
|
||||
AU_CLASS( tstb, TEST_C3X )
|
||||
T2C_CLASS( tstb, TEST_C3X )
|
||||
AU_CLASS( xor, TEST_C3X )
|
||||
TC_CLASS( xor, TEST_C3X )
|
||||
QC_CLASS( xor, sti, TEST_C3X )
|
||||
|
||||
;;------------------------------------
|
||||
;; C4X INSNS
|
||||
;;------------------------------------
|
||||
.ifdef TEST_C4X
|
||||
J_CLASS( bCaf, baf )
|
||||
J_CLASS( bCat, bat )
|
||||
B6_CLASS( frieee )
|
||||
P_CLASS( frieee, stf )
|
||||
J_CLASS( bCaf, baf, TEST_C4X )
|
||||
J_CLASS( bCat, bat, TEST_C4X )
|
||||
B6_CLASS( frieee, TEST_C4X )
|
||||
P_CLASS( frieee, stf, TEST_C4X )
|
||||
.ifdef TEST_C4X
|
||||
laj_I: laj start
|
||||
laj_JS: lajc R0
|
||||
lajc start
|
||||
lat_Z: latC 10
|
||||
A_CLASS( lb0 )
|
||||
A_CLASS( lb1 )
|
||||
A_CLASS( lb2 )
|
||||
A_CLASS( lb3 )
|
||||
AU_CLASS( lbu0 )
|
||||
AU_CLASS( lbu1 )
|
||||
AU_CLASS( lbu2 )
|
||||
AU_CLASS( lbu3 )
|
||||
AY_CLASS( lda )
|
||||
.endif
|
||||
A_CLASS( lb0, TEST_C4X )
|
||||
A_CLASS( lb1, TEST_C4X )
|
||||
A_CLASS( lb2, TEST_C4X )
|
||||
A_CLASS( lb3, TEST_C4X )
|
||||
AU_CLASS( lbu0, TEST_C4X )
|
||||
AU_CLASS( lbu1, TEST_C4X )
|
||||
AU_CLASS( lbu2, TEST_C4X )
|
||||
AU_CLASS( lbu3, TEST_C4X )
|
||||
AY_CLASS( lda, TEST_C4X )
|
||||
.ifdef TEST_C4X
|
||||
ldep_Z: ldep IVTP, AR0
|
||||
ldhi_Z: ldhi 35, R0
|
||||
ldhi start, R0
|
||||
ldpe_Z: ldpe AR0, IVTP
|
||||
ldpk_Z: ldpk start
|
||||
A_CLASS( lh0 )
|
||||
A_CLASS( lh1 )
|
||||
AU_CLASS( lhu0 )
|
||||
AU_CLASS( lhu1 )
|
||||
A_CLASS( lwl0 )
|
||||
A_CLASS( lwl1 )
|
||||
A_CLASS( lwl2 )
|
||||
A_CLASS( lwl3 )
|
||||
A_CLASS( lwr0 )
|
||||
A_CLASS( lwr1 )
|
||||
A_CLASS( lwr2 )
|
||||
A_CLASS( lwr3 )
|
||||
A_CLASS( mb0 )
|
||||
A_CLASS( mb1 )
|
||||
A_CLASS( mb2 )
|
||||
A_CLASS( mb3 )
|
||||
A_CLASS( mh0 )
|
||||
A_CLASS( mh1 )
|
||||
A_CLASS( mh2 )
|
||||
A_CLASS( mh3 )
|
||||
A_CLASS( mpyshi )
|
||||
TC_CLASS( mpyshi )
|
||||
A_CLASS( mpyuhi )
|
||||
TC_CLASS( mpyuhi )
|
||||
BA_CLASS( rcpf )
|
||||
.endif
|
||||
A_CLASS( lh0, TEST_C4X )
|
||||
A_CLASS( lh1, TEST_C4X )
|
||||
AU_CLASS( lhu0, TEST_C4X )
|
||||
AU_CLASS( lhu1, TEST_C4X )
|
||||
A_CLASS( lwl0, TEST_C4X )
|
||||
A_CLASS( lwl1, TEST_C4X )
|
||||
A_CLASS( lwl2, TEST_C4X )
|
||||
A_CLASS( lwl3, TEST_C4X )
|
||||
A_CLASS( lwr0, TEST_C4X )
|
||||
A_CLASS( lwr1, TEST_C4X )
|
||||
A_CLASS( lwr2, TEST_C4X )
|
||||
A_CLASS( lwr3, TEST_C4X )
|
||||
A_CLASS( mb0, TEST_C4X )
|
||||
A_CLASS( mb1, TEST_C4X )
|
||||
A_CLASS( mb2, TEST_C4X )
|
||||
A_CLASS( mb3, TEST_C4X )
|
||||
A_CLASS( mh0, TEST_C4X )
|
||||
A_CLASS( mh1, TEST_C4X )
|
||||
A_CLASS( mh2, TEST_C4X )
|
||||
A_CLASS( mh3, TEST_C4X )
|
||||
A_CLASS( mpyshi, TEST_C4X )
|
||||
TC_CLASS( mpyshi, TEST_C4X )
|
||||
A_CLASS( mpyuhi, TEST_C4X )
|
||||
TC_CLASS( mpyuhi, TEST_C4X )
|
||||
BA_CLASS( rcpf, TEST_C4X )
|
||||
.ifdef TEST_C4X
|
||||
retid_Z: retiCd
|
||||
retid
|
||||
rptb2_I2: rptb AR0
|
||||
rptbd_I2: rptbd start
|
||||
rptbd AR0
|
||||
B_CLASS( rsqrf )
|
||||
A6_CLASS( sigi )
|
||||
.endif
|
||||
B_CLASS( rsqrf, TEST_C4X )
|
||||
A6_CLASS( sigi, TEST_C4X )
|
||||
.ifdef TEST_C4X
|
||||
sti2_A7: sti -5, @start
|
||||
sti -5, *+AR0(5)
|
||||
stik_Z: stik -5, @start
|
||||
stik -5, *+AR0(5)
|
||||
B_CLASS( toieee )
|
||||
P_CLASS( toieee, stf )
|
||||
.endif
|
||||
B_CLASS( toieee, TEST_C4X )
|
||||
P_CLASS( toieee, stf, TEST_C4X )
|
||||
.endif
|
||||
.end
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -535,7 +535,7 @@ Disassembly of section .text:
|
|||
16e: 83000001.*
|
||||
16f: 83020001.*
|
||||
|
||||
00000170 <addf3_mpyf3_M>:
|
||||
00000170 <addf3_mpyf_M>:
|
||||
170: 80080100.*
|
||||
171: 80100100.*
|
||||
172: 81000001.*
|
||||
|
|
@ -565,7 +565,7 @@ Disassembly of section .text:
|
|||
188: 83000001.*
|
||||
189: 83020001.*
|
||||
|
||||
0000018a <addf3_mpyf_M>:
|
||||
0000018a <addf3_mpyf3_M>:
|
||||
18a: 80080100.*
|
||||
18b: 80100100.*
|
||||
18c: 81000001.*
|
||||
|
|
@ -671,7 +671,7 @@ Disassembly of section .text:
|
|||
1e2: 87000001.*
|
||||
1e3: 87020001.*
|
||||
|
||||
000001e4 <subf3_mpyf3_M>:
|
||||
000001e4 <subf3_mpyf_M>:
|
||||
1e4: 84080100.*
|
||||
1e5: 84100100.*
|
||||
1e6: 85000001.*
|
||||
|
|
@ -701,7 +701,7 @@ Disassembly of section .text:
|
|||
1fc: 87000001.*
|
||||
1fd: 87020001.*
|
||||
|
||||
000001fe <subf3_mpyf_M>:
|
||||
000001fe <subf3_mpyf3_M>:
|
||||
1fe: 84080100.*
|
||||
1ff: 84100100.*
|
||||
200: 85000001.*
|
||||
|
|
@ -814,7 +814,7 @@ Disassembly of section .text:
|
|||
25b: 8b000001.*
|
||||
25c: 8b020001.*
|
||||
|
||||
0000025d <addi3_mpyi3_M>:
|
||||
0000025d <addi3_mpyi_M>:
|
||||
25d: 88080100.*
|
||||
25e: 88100100.*
|
||||
25f: 89000001.*
|
||||
|
|
@ -844,7 +844,7 @@ Disassembly of section .text:
|
|||
275: 8b000001.*
|
||||
276: 8b020001.*
|
||||
|
||||
00000277 <addi3_mpyi_M>:
|
||||
00000277 <addi3_mpyi3_M>:
|
||||
277: 88080100.*
|
||||
278: 88100100.*
|
||||
279: 89000001.*
|
||||
|
|
@ -950,7 +950,7 @@ Disassembly of section .text:
|
|||
2cf: 8f000001.*
|
||||
2d0: 8f020001.*
|
||||
|
||||
000002d1 <subi3_mpyi3_M>:
|
||||
000002d1 <subi3_mpyi_M>:
|
||||
2d1: 8c080100.*
|
||||
2d2: 8c100100.*
|
||||
2d3: 8d000001.*
|
||||
|
|
@ -980,7 +980,7 @@ Disassembly of section .text:
|
|||
2e9: 8f000001.*
|
||||
2ea: 8f020001.*
|
||||
|
||||
000002eb <subi3_mpyi_M>:
|
||||
000002eb <subi3_mpyi3_M>:
|
||||
2eb: 8c080100.*
|
||||
2ec: 8c100100.*
|
||||
2ed: 8d000001.*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
#as: -m40 --defsym TEST_C4X=1
|
||||
#as: -m40 --defsym TEST_C4X=1 --defsym TEST_C3X=1
|
||||
#objdump: -d -z
|
||||
#name: c4x opcodes
|
||||
#source: opcodes.s
|
||||
|
|
@ -43,13 +43,15 @@ Disassembly of section .text:
|
|||
16: 20480900.*
|
||||
17: 01480001.*
|
||||
18: 20680001.*
|
||||
19: 30080905.*
|
||||
1a: 01680005.*
|
||||
|
||||
00000019 <addc_TC_c4x>:
|
||||
19: 300809fb.*
|
||||
1a: 0168fffb.*
|
||||
1b: 300809fb.*
|
||||
1c: 30280928.*
|
||||
1d: 01480005.*
|
||||
1e: 30280928.*
|
||||
1f: 30482805.*
|
||||
1f: 304828fb.*
|
||||
20: 304828fb.*
|
||||
21: 30682928.*
|
||||
|
||||
|
|
@ -60,6 +62,8 @@ Disassembly of section .text:
|
|||
25: 20480900.*
|
||||
26: 20480800.*
|
||||
27: 20680001.*
|
||||
|
||||
00000028 <addc3_TC_c4x>:
|
||||
28: 300809fb.*
|
||||
29: 300808fb.*
|
||||
2a: 300809fb.*
|
||||
|
|
@ -84,6 +88,8 @@ Disassembly of section .text:
|
|||
39: 20c00100.*
|
||||
3a: 01c00001.*
|
||||
3b: 20e00100.*
|
||||
|
||||
0000003c <addf_SC_c4x>:
|
||||
3c: 30a00128.*
|
||||
3d: 01c00005.*
|
||||
3e: 30a00128.*
|
||||
|
|
@ -96,6 +102,8 @@ Disassembly of section .text:
|
|||
43: 20c00100.*
|
||||
44: 20c00000.*
|
||||
45: 20e00100.*
|
||||
|
||||
00000046 <addf3_SC_c4x>:
|
||||
46: 30a00128.*
|
||||
47: 30a00028.*
|
||||
48: 30a00128.*
|
||||
|
|
@ -131,13 +139,15 @@ Disassembly of section .text:
|
|||
5e: 21480900.*
|
||||
5f: 02480001.*
|
||||
60: 21680001.*
|
||||
61: 31080905.*
|
||||
62: 02680005.*
|
||||
|
||||
00000061 <addi_TC_c4x>:
|
||||
61: 310809fb.*
|
||||
62: 0268fffb.*
|
||||
63: 310809fb.*
|
||||
64: 31280928.*
|
||||
65: 02480005.*
|
||||
66: 31280928.*
|
||||
67: 31482805.*
|
||||
67: 314828fb.*
|
||||
68: 314828fb.*
|
||||
69: 31682928.*
|
||||
|
||||
|
|
@ -148,6 +158,8 @@ Disassembly of section .text:
|
|||
6d: 21480900.*
|
||||
6e: 21480800.*
|
||||
6f: 21680001.*
|
||||
|
||||
00000070 <addi3_TC_c4x>:
|
||||
70: 310809fb.*
|
||||
71: 310808fb.*
|
||||
72: 310809fb.*
|
||||
|
|
@ -188,13 +200,15 @@ Disassembly of section .text:
|
|||
8d: 21c80900.*
|
||||
8e: 02c80001.*
|
||||
8f: 21e80001.*
|
||||
90: 31880905.*
|
||||
91: 02e80005.*
|
||||
|
||||
00000090 <and_TC_c4x>:
|
||||
90: 318809fb.*
|
||||
91: 318808fb.*
|
||||
92: 318809fb.*
|
||||
93: 31a80928.*
|
||||
94: 02c80005.*
|
||||
95: 31a80928.*
|
||||
96: 31c82805.*
|
||||
96: 31c828fb.*
|
||||
97: 31c828fb.*
|
||||
98: 31e82928.*
|
||||
|
||||
|
|
@ -205,6 +219,8 @@ Disassembly of section .text:
|
|||
9c: 21c80900.*
|
||||
9d: 21c80800.*
|
||||
9e: 21e80001.*
|
||||
|
||||
0000009f <and3_TC_c4x>:
|
||||
9f: 318809fb.*
|
||||
a0: 318808fb.*
|
||||
a1: 318809fb.*
|
||||
|
|
@ -245,11 +261,13 @@ Disassembly of section .text:
|
|||
bc: 22480900.*
|
||||
bd: 03480001.*
|
||||
be: 22680001.*
|
||||
bf: 32080905.*
|
||||
c0: 03680005.*
|
||||
|
||||
000000bf <andn_T_sc>:
|
||||
bf: 320809fb.*
|
||||
c0: 320808fb.*
|
||||
c1: 32280928.*
|
||||
c2: 03480005.*
|
||||
c3: 32482805.*
|
||||
c3: 324828fb.*
|
||||
c4: 32682928.*
|
||||
|
||||
000000c5 <andn3_T>:
|
||||
|
|
@ -259,6 +277,8 @@ Disassembly of section .text:
|
|||
c8: 22480900.*
|
||||
c9: 22480800.*
|
||||
ca: 22680001.*
|
||||
|
||||
000000cb <andn3_T_sc>:
|
||||
cb: 320809fb.*
|
||||
cc: 320808fb.*
|
||||
cd: 32280928.*
|
||||
|
|
@ -280,11 +300,13 @@ Disassembly of section .text:
|
|||
d9: 22c80900.*
|
||||
da: 03c80001.*
|
||||
db: 22e80001.*
|
||||
dc: 32880905.*
|
||||
dd: 03e80005.*
|
||||
|
||||
000000dc <ash_T_sc>:
|
||||
dc: 328809fb.*
|
||||
dd: 03e8fffb.*
|
||||
de: 32a80928.*
|
||||
df: 03c80005.*
|
||||
e0: 32c82805.*
|
||||
e0: 32c828fb.*
|
||||
e1: 32e82928.*
|
||||
|
||||
000000e2 <ash3_T>:
|
||||
|
|
@ -294,6 +316,8 @@ Disassembly of section .text:
|
|||
e5: 22c80900.*
|
||||
e6: 22c80800.*
|
||||
e7: 22e80001.*
|
||||
|
||||
000000e8 <ash3_T_sc>:
|
||||
e8: 328809fb.*
|
||||
e9: 328808fb.*
|
||||
ea: 32a80928.*
|
||||
|
|
@ -350,6 +374,8 @@ Disassembly of section .text:
|
|||
105: 23200001.*
|
||||
106: 04410001.*
|
||||
107: 23600100.*
|
||||
|
||||
00000108 <cmpf_S2_c4x>:
|
||||
108: 04410005.*
|
||||
109: 33602928.*
|
||||
|
||||
|
|
@ -358,6 +384,8 @@ Disassembly of section .text:
|
|||
10b: 23200001.*
|
||||
10c: 23400100.*
|
||||
10d: 23600100.*
|
||||
|
||||
0000010e <cmpf3_S2_c4x>:
|
||||
10e: 33200128.*
|
||||
10f: 33602928.*
|
||||
|
||||
|
|
@ -373,6 +401,8 @@ Disassembly of section .text:
|
|||
116: 23a00009.*
|
||||
117: 04c90001.*
|
||||
118: 23e00001.*
|
||||
|
||||
00000119 <cmpi_T2_c4x>:
|
||||
119: 04e9fffb.*
|
||||
11a: 04c90005.*
|
||||
11b: 33c028fb.*
|
||||
|
|
@ -383,6 +413,8 @@ Disassembly of section .text:
|
|||
11e: 23a00009.*
|
||||
11f: 23c00900.*
|
||||
120: 23e00001.*
|
||||
|
||||
00000121 <cmpi3_T2_c4x>:
|
||||
121: 338009fb.*
|
||||
122: 33a00928.*
|
||||
123: 33c028fb.*
|
||||
|
|
@ -518,11 +550,13 @@ Disassembly of section .text:
|
|||
173: 24480900.*
|
||||
174: 09c80001.*
|
||||
175: 24680001.*
|
||||
176: 34080905.*
|
||||
177: 09e80005.*
|
||||
|
||||
00000176 <lsh_T_sc>:
|
||||
176: 340809fb.*
|
||||
177: 09e8fffb.*
|
||||
178: 34280928.*
|
||||
179: 09c80005.*
|
||||
17a: 34482805.*
|
||||
17a: 344828fb.*
|
||||
17b: 34682928.*
|
||||
|
||||
0000017c <lsh3_T>:
|
||||
|
|
@ -532,6 +566,8 @@ Disassembly of section .text:
|
|||
17f: 24480900.*
|
||||
180: 24480800.*
|
||||
181: 24680001.*
|
||||
|
||||
00000182 <lsh3_T_sc>:
|
||||
182: 340809fb.*
|
||||
183: 340808fb.*
|
||||
184: 34280928.*
|
||||
|
|
@ -561,6 +597,8 @@ Disassembly of section .text:
|
|||
194: 24c00100.*
|
||||
195: 0a400001.*
|
||||
196: 24e00100.*
|
||||
|
||||
00000197 <mpyf_SC_c4x>:
|
||||
197: 34a00128.*
|
||||
198: 0a400005.*
|
||||
199: 34a00128.*
|
||||
|
|
@ -573,6 +611,8 @@ Disassembly of section .text:
|
|||
19e: 24c00100.*
|
||||
19f: 24c00000.*
|
||||
1a0: 24e00100.*
|
||||
|
||||
000001a1 <mpyf3_SC_c4x>:
|
||||
1a1: 34a00128.*
|
||||
1a2: 34a00028.*
|
||||
1a3: 34a00128.*
|
||||
|
|
@ -653,7 +693,7 @@ Disassembly of section .text:
|
|||
1e4: 83000001.*
|
||||
1e5: 83020001.*
|
||||
|
||||
000001e6 <addf3_mpyf3_M>:
|
||||
000001e6 <addf3_mpyf_M>:
|
||||
1e6: 80080100.*
|
||||
1e7: 80100100.*
|
||||
1e8: 81000001.*
|
||||
|
|
@ -683,7 +723,7 @@ Disassembly of section .text:
|
|||
1fe: 83000001.*
|
||||
1ff: 83020001.*
|
||||
|
||||
00000200 <addf3_mpyf_M>:
|
||||
00000200 <addf3_mpyf3_M>:
|
||||
200: 80080100.*
|
||||
201: 80100100.*
|
||||
202: 81000001.*
|
||||
|
|
@ -789,7 +829,7 @@ Disassembly of section .text:
|
|||
258: 87000001.*
|
||||
259: 87020001.*
|
||||
|
||||
0000025a <subf3_mpyf3_M>:
|
||||
0000025a <subf3_mpyf_M>:
|
||||
25a: 84080100.*
|
||||
25b: 84100100.*
|
||||
25c: 85000001.*
|
||||
|
|
@ -819,7 +859,7 @@ Disassembly of section .text:
|
|||
272: 87000001.*
|
||||
273: 87020001.*
|
||||
|
||||
00000274 <subf3_mpyf_M>:
|
||||
00000274 <subf3_mpyf3_M>:
|
||||
274: 84080100.*
|
||||
275: 84100100.*
|
||||
276: 85000001.*
|
||||
|
|
@ -848,13 +888,15 @@ Disassembly of section .text:
|
|||
289: 25480900.*
|
||||
28a: 0ac80001.*
|
||||
28b: 25680001.*
|
||||
28c: 35080905.*
|
||||
28d: 0ae80005.*
|
||||
|
||||
0000028c <mpyi_TC_c4x>:
|
||||
28c: 350809fb.*
|
||||
28d: 0ae8fffb.*
|
||||
28e: 350809fb.*
|
||||
28f: 35280928.*
|
||||
290: 0ac80005.*
|
||||
291: 35280928.*
|
||||
292: 35482805.*
|
||||
292: 354828fb.*
|
||||
293: 354828fb.*
|
||||
294: 35682928.*
|
||||
|
||||
|
|
@ -865,6 +907,8 @@ Disassembly of section .text:
|
|||
298: 25480900.*
|
||||
299: 25480800.*
|
||||
29a: 25680001.*
|
||||
|
||||
0000029b <mpyi3_TC_c4x>:
|
||||
29b: 350809fb.*
|
||||
29c: 350808fb.*
|
||||
29d: 350809fb.*
|
||||
|
|
@ -950,7 +994,7 @@ Disassembly of section .text:
|
|||
2e3: 8b000001.*
|
||||
2e4: 8b020001.*
|
||||
|
||||
000002e5 <addi3_mpyi3_M>:
|
||||
000002e5 <addi3_mpyi_M>:
|
||||
2e5: 88080100.*
|
||||
2e6: 88100100.*
|
||||
2e7: 89000001.*
|
||||
|
|
@ -980,7 +1024,7 @@ Disassembly of section .text:
|
|||
2fd: 8b000001.*
|
||||
2fe: 8b020001.*
|
||||
|
||||
000002ff <addi3_mpyi_M>:
|
||||
000002ff <addi3_mpyi3_M>:
|
||||
2ff: 88080100.*
|
||||
300: 88100100.*
|
||||
301: 89000001.*
|
||||
|
|
@ -1086,7 +1130,7 @@ Disassembly of section .text:
|
|||
357: 8f000001.*
|
||||
358: 8f020001.*
|
||||
|
||||
00000359 <subi3_mpyi3_M>:
|
||||
00000359 <subi3_mpyi_M>:
|
||||
359: 8c080100.*
|
||||
35a: 8c100100.*
|
||||
35b: 8d000001.*
|
||||
|
|
@ -1116,7 +1160,7 @@ Disassembly of section .text:
|
|||
371: 8f000001.*
|
||||
372: 8f020001.*
|
||||
|
||||
00000373 <subi3_mpyi_M>:
|
||||
00000373 <subi3_mpyi3_M>:
|
||||
373: 8c080100.*
|
||||
374: 8c100100.*
|
||||
375: 8d000001.*
|
||||
|
|
@ -1197,13 +1241,15 @@ Disassembly of section .text:
|
|||
3aa: 25c80900.*
|
||||
3ab: 10480001.*
|
||||
3ac: 25e80001.*
|
||||
3ad: 35880905.*
|
||||
3ae: 10680005.*
|
||||
|
||||
000003ad <or_TC_c4x>:
|
||||
3ad: 358809fb.*
|
||||
3ae: 358808fb.*
|
||||
3af: 358809fb.*
|
||||
3b0: 35a80928.*
|
||||
3b1: 10480005.*
|
||||
3b2: 35a80928.*
|
||||
3b3: 35c82805.*
|
||||
3b3: 35c828fb.*
|
||||
3b4: 35c828fb.*
|
||||
3b5: 35e82928.*
|
||||
|
||||
|
|
@ -1214,6 +1260,8 @@ Disassembly of section .text:
|
|||
3b9: 25c80900.*
|
||||
3ba: 25c80800.*
|
||||
3bb: 25e80001.*
|
||||
|
||||
000003bc <or3_TC_c4x>:
|
||||
3bc: 358809fb.*
|
||||
3bd: 358808fb.*
|
||||
3be: 358809fb.*
|
||||
|
|
@ -1331,11 +1379,13 @@ Disassembly of section .text:
|
|||
3fe: 26480900.*
|
||||
3ff: 16c80001.*
|
||||
400: 26680001.*
|
||||
401: 36080905.*
|
||||
402: 16e80005.*
|
||||
|
||||
00000401 <subb_T_sc>:
|
||||
401: 360809fb.*
|
||||
402: 16e8fffb.*
|
||||
403: 36280928.*
|
||||
404: 16c80005.*
|
||||
405: 36482805.*
|
||||
405: 364828fb.*
|
||||
406: 36682928.*
|
||||
|
||||
00000407 <subb3_T>:
|
||||
|
|
@ -1345,6 +1395,8 @@ Disassembly of section .text:
|
|||
40a: 26480900.*
|
||||
40b: 26480800.*
|
||||
40c: 26680001.*
|
||||
|
||||
0000040d <subb3_T_sc>:
|
||||
40d: 360809fb.*
|
||||
40e: 360808fb.*
|
||||
40f: 36280928.*
|
||||
|
|
@ -1373,6 +1425,8 @@ Disassembly of section .text:
|
|||
420: 26c00100.*
|
||||
421: 17c00001.*
|
||||
422: 26e00100.*
|
||||
|
||||
00000423 <subf_S_c4x>:
|
||||
423: 36a00128.*
|
||||
424: 17c00005.*
|
||||
425: 36e02928.*
|
||||
|
|
@ -1384,6 +1438,8 @@ Disassembly of section .text:
|
|||
429: 26c00100.*
|
||||
42a: 26c00000.*
|
||||
42b: 26e00100.*
|
||||
|
||||
0000042c <subf3_S_c4x>:
|
||||
42c: 36a00128.*
|
||||
42d: 36a00028.*
|
||||
42e: 36e02928.*
|
||||
|
|
@ -1410,11 +1466,13 @@ Disassembly of section .text:
|
|||
43b: 27480900.*
|
||||
43c: 18480001.*
|
||||
43d: 27680001.*
|
||||
43e: 37080905.*
|
||||
43f: 18680005.*
|
||||
|
||||
0000043e <subi_T_sc>:
|
||||
43e: 370809fb.*
|
||||
43f: 1868fffb.*
|
||||
440: 37280928.*
|
||||
441: 18480005.*
|
||||
442: 37482805.*
|
||||
442: 374828fb.*
|
||||
443: 37682928.*
|
||||
|
||||
00000444 <subi3_T>:
|
||||
|
|
@ -1424,6 +1482,8 @@ Disassembly of section .text:
|
|||
447: 27480900.*
|
||||
448: 27480800.*
|
||||
449: 27680001.*
|
||||
|
||||
0000044a <subi3_T_sc>:
|
||||
44a: 370809fb.*
|
||||
44b: 370808fb.*
|
||||
44c: 37280928.*
|
||||
|
|
@ -1479,11 +1539,13 @@ Disassembly of section .text:
|
|||
46c: 27a00009.*
|
||||
46d: 1a490001.*
|
||||
46e: 27e00001.*
|
||||
46f: 1a690005.*
|
||||
|
||||
0000046f <tstb_T2C_c4x>:
|
||||
46f: 378009fb.*
|
||||
470: 378009fb.*
|
||||
471: 1a490005.*
|
||||
472: 37a00928.*
|
||||
473: 37c02805.*
|
||||
473: 37c028fb.*
|
||||
474: 37c028fb.*
|
||||
475: 37e02928.*
|
||||
|
||||
|
|
@ -1492,6 +1554,8 @@ Disassembly of section .text:
|
|||
477: 27a00009.*
|
||||
478: 27c00900.*
|
||||
479: 27e00001.*
|
||||
|
||||
0000047a <tstb3_T2C_c4x>:
|
||||
47a: 378009fb.*
|
||||
47b: 378009fb.*
|
||||
47c: 37a00928.*
|
||||
|
|
@ -1514,13 +1578,15 @@ Disassembly of section .text:
|
|||
489: 28480900.*
|
||||
48a: 1ac80001.*
|
||||
48b: 28680001.*
|
||||
48c: 38080905.*
|
||||
48d: 1ae80005.*
|
||||
|
||||
0000048c <xor_TC_c4x>:
|
||||
48c: 380809fb.*
|
||||
48d: 380808fb.*
|
||||
48e: 380809fb.*
|
||||
48f: 38280928.*
|
||||
490: 1ac80005.*
|
||||
491: 38280928.*
|
||||
492: 38482805.*
|
||||
492: 384828fb.*
|
||||
493: 384828fb.*
|
||||
494: 38682928.*
|
||||
|
||||
|
|
@ -1531,6 +1597,8 @@ Disassembly of section .text:
|
|||
498: 28480900.*
|
||||
499: 28480800.*
|
||||
49a: 28680001.*
|
||||
|
||||
0000049b <xor3_TC_c4x>:
|
||||
49b: 380809fb.*
|
||||
49c: 380808fb.*
|
||||
49d: 380809fb.*
|
||||
|
|
@ -1820,13 +1888,15 @@ Disassembly of section .text:
|
|||
55d: 28c80900.*
|
||||
55e: 1dc80001.*
|
||||
55f: 28e80001.*
|
||||
560: 38880905.*
|
||||
561: 1de80005.*
|
||||
|
||||
00000560 <mpyshi_TC_c4x>:
|
||||
560: 388809fb.*
|
||||
561: 1de8fffb.*
|
||||
562: 388809fb.*
|
||||
563: 38a80928.*
|
||||
564: 1dc80005.*
|
||||
565: 38a80928.*
|
||||
566: 38c82805.*
|
||||
566: 38c828fb.*
|
||||
567: 38c828fb.*
|
||||
568: 38e82928.*
|
||||
|
||||
|
|
@ -1837,6 +1907,8 @@ Disassembly of section .text:
|
|||
56c: 28c80900.*
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -1861,13 +1933,15 @@ Disassembly of section .text:
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
|
|
@ -1878,6 +1952,8 @@ Disassembly of section .text:
|
|||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
|
|
|||
|
|
@ -0,0 +1,767 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
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|
||||
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||||
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|
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||||
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||||
|
||||
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|
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211: 8c12e0e0.*
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220: e40101e0.*
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221: e40101e0.*
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222: e40101e0.*
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|
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|
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|
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|
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|
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242: c20101e0.*
|
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243: c20101e0.*
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244: c20101e0.*
|
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245: c20101e0.*
|
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246: c20101e0.*
|
||||
|
||||
00000247 <subf_stf_Q_enh>:
|
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|
||||
248: ea0101e0.*
|
||||
249: ea0101e0.*
|
||||
24a: ea0101e0.*
|
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|
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|
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|
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|
||||
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|
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|
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|
||||
251: ec0101e0.*
|
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252: ec0101e0.*
|
||||
|
||||
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|
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|
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|
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|
||||
26a: ee0101e8.*
|
||||
|
|
@ -57,6 +57,7 @@ if [istarget *c4x*-*-*] then {
|
|||
# Test float instructions
|
||||
run_dump_test "opcodes_c3x"
|
||||
run_dump_test "opcodes_c4x"
|
||||
run_dump_test "opcodes_new"
|
||||
|
||||
# Make sure the c4x ops dont work on c3x
|
||||
#gas_test_error "opcodes.s" "-m30 --defsym TEST_C4X=1" "c4x instruction usage in c3x"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
|
||||
|
||||
* opcode/tic4x.h: File reordering. Added enhanced opcodes.
|
||||
|
||||
2002-11-16 Klee Dienes <kdienes@apple.com>
|
||||
|
||||
* opcode/m88k.h (INSTAB): Remove 'next' field.
|
||||
|
|
|
|||
|
|
@ -129,6 +129,97 @@ static const c4x_register_t c4x_registers[] =
|
|||
|
||||
const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
|
||||
|
||||
struct c4x_cond
|
||||
{
|
||||
char * name;
|
||||
unsigned long cond;
|
||||
};
|
||||
|
||||
typedef struct c4x_cond c4x_cond_t;
|
||||
|
||||
/* Define conditional branch/load suffixes. Put desired form for
|
||||
disassembler last. */
|
||||
static const c4x_cond_t c4x_conds[] =
|
||||
{
|
||||
{ "u", 0x00 },
|
||||
{ "c", 0x01 }, { "lo", 0x01 },
|
||||
{ "ls", 0x02 },
|
||||
{ "hi", 0x03 },
|
||||
{ "nc", 0x04 }, { "hs", 0x04 },
|
||||
{ "z", 0x05 }, { "eq", 0x05 },
|
||||
{ "nz", 0x06 }, { "ne", 0x06 },
|
||||
{ "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
|
||||
{ "le", 0x08 },
|
||||
{ "p", 0x09 }, { "gt", 0x09 },
|
||||
{ "nn", 0x0a }, { "ge", 0x0a },
|
||||
{ "nv", 0x0c },
|
||||
{ "v", 0x0d },
|
||||
{ "nuf", 0x0e },
|
||||
{ "uf", 0x0f },
|
||||
{ "nlv", 0x10 },
|
||||
{ "lv", 0x11 },
|
||||
{ "nluf", 0x12 },
|
||||
{ "luf", 0x13 },
|
||||
{ "zuf", 0x14 },
|
||||
/* Dummy entry, not included in num_conds. This
|
||||
lets code examine entry i+1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0}
|
||||
};
|
||||
|
||||
const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
|
||||
|
||||
struct c4x_indirect
|
||||
{
|
||||
char * name;
|
||||
unsigned long modn;
|
||||
};
|
||||
|
||||
typedef struct c4x_indirect c4x_indirect_t;
|
||||
|
||||
/* Define indirect addressing modes where:
|
||||
d displacement (signed)
|
||||
y ir0
|
||||
z ir1 */
|
||||
|
||||
static const c4x_indirect_t c4x_indirects[] =
|
||||
{
|
||||
{ "*+a(d)", 0x00 },
|
||||
{ "*-a(d)", 0x01 },
|
||||
{ "*++a(d)", 0x02 },
|
||||
{ "*--a(d)", 0x03 },
|
||||
{ "*a++(d)", 0x04 },
|
||||
{ "*a--(d)", 0x05 },
|
||||
{ "*a++(d)%", 0x06 },
|
||||
{ "*a--(d)%", 0x07 },
|
||||
{ "*+a(y)", 0x08 },
|
||||
{ "*-a(y)", 0x09 },
|
||||
{ "*++a(y)", 0x0a },
|
||||
{ "*--a(y)", 0x0b },
|
||||
{ "*a++(y)", 0x0c },
|
||||
{ "*a--(y)", 0x0d },
|
||||
{ "*a++(y)%", 0x0e },
|
||||
{ "*a--(y)%", 0x0f },
|
||||
{ "*+a(z)", 0x10 },
|
||||
{ "*-a(z)", 0x11 },
|
||||
{ "*++a(z)", 0x12 },
|
||||
{ "*--a(z)", 0x13 },
|
||||
{ "*a++(z)", 0x14 },
|
||||
{ "*a--(z)", 0x15 },
|
||||
{ "*a++(z)%", 0x16 },
|
||||
{ "*a--(z)%", 0x17 },
|
||||
{ "*a", 0x18 },
|
||||
{ "*a++(y)b", 0x19 },
|
||||
/* Dummy entry, not included in num_indirects. This
|
||||
lets code examine entry i+1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0}
|
||||
};
|
||||
|
||||
#define C3X_MODN_MAX 0x19
|
||||
|
||||
const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
|
||||
|
||||
/* Instruction template. */
|
||||
struct c4x_inst
|
||||
{
|
||||
|
|
@ -163,8 +254,10 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
|
||||
g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
|
||||
H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
|
||||
I indirect (no disp) 0--7 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
|
||||
J indirect (no disp) 8--15 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
|
||||
I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
|
||||
i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5
|
||||
J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
|
||||
j indirect (enhanced) 8--15 [M] - *+AR0(1), R5
|
||||
K register 19--21 [LL,M,Q,QC] - R0, R7
|
||||
L register 22--24 [LL,LS,P,Q,QC] - R0, R7
|
||||
M register (R2,R3) 22--22 [M] R2, R3
|
||||
|
|
@ -189,15 +282,15 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */
|
||||
|
||||
/* Define the instruction level */
|
||||
#define OP_C3X 0x0 /* C30 support - supported by all */
|
||||
#define OP_C4X 0x1 /* C40 support - C40, C44 */
|
||||
#define OP_C3XE 0x2 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
|
||||
I and J is enhanced in these classes - C31>=6.0,
|
||||
C32>=2.0, C33 */
|
||||
#define OP_LPWR 0x3 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
|
||||
LC31, C31>=5.0, C32 */
|
||||
#define OP_IDLE 0x4 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
|
||||
C32, C33, C40>=5.0, C44 */
|
||||
#define OP_C3X 0x1 /* C30 support - supported by all */
|
||||
#define OP_C4X 0x2 /* C40 support - C40, C44 */
|
||||
#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
|
||||
I and J is enhanced in these classes - C31>=6.0,
|
||||
C32>=2.0, C33 */
|
||||
#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
|
||||
LC31, C31>=5.0, C32 */
|
||||
#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
|
||||
C32, C33, C40>=5.0, C44 */
|
||||
|
||||
/* The following class definition is a classification scheme for
|
||||
putting instructions with similar type of arguments together. It
|
||||
|
|
@ -430,29 +523,29 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
Syntax: <i> src2, dst2 || <i> src1, dst1
|
||||
src1 = Indirect 0,1,IR0,IR1 (J)
|
||||
dst1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
|
||||
dst2 = Register 0-7 (L)
|
||||
Instr: 2/0 - LDF||LDF, LDI||LDI
|
||||
Alias: i||i, i1||i2, i2||i1
|
||||
*/
|
||||
#define LL_CLASS_INSN(name, opcode, level) \
|
||||
{ name "_" name , opcode, 0xfe000000, "I,L|J,K", level }, \
|
||||
{ name "2_" name "1", opcode, 0xfe000000, "I,L|J,K", level }, \
|
||||
{ name "1_" name "2", opcode, 0xfe000000, "J,K|I,L", level }
|
||||
{ name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \
|
||||
{ name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
|
||||
{ name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
|
||||
|
||||
/* LS: Store-store parallell operation
|
||||
Syntax: <i> src2, dst2 || <i> src1, dst1
|
||||
src1 = Register 0-7 (H)
|
||||
dst1 = Indirect 0,1,IR0,IR1 (J)
|
||||
src2 = Register 0-7 (L)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
|
||||
Instr: 2/0 - STF||STF, STI||STI
|
||||
Alias: i||i, i1||i2, i2||i1.
|
||||
*/
|
||||
#define LS_CLASS_INSN(name, opcode, level) \
|
||||
{ name "_" name , opcode, 0xfe000000, "L,I|H,J", level }, \
|
||||
{ name "2_" name "1", opcode, 0xfe000000, "L,I|H,J", level }, \
|
||||
{ name "1_" name "2", opcode, 0xfe000000, "H,J|L,I", level }
|
||||
{ name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \
|
||||
{ name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
|
||||
{ name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
|
||||
|
||||
/* M: General multiply and add/sub operations
|
||||
Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
|
||||
|
|
@ -463,66 +556,66 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
<ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Register 0-7 (H)
|
||||
src3 = Indirect 0,1,IR0,IR1 (J)
|
||||
src4 = Indirect 0,1,IR0,IR1 (I)
|
||||
src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
|
||||
src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
|
||||
dst1 = Register 0-1 (N)
|
||||
dst2 = Register 2-3 (M)
|
||||
Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
|
||||
Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
|
||||
*/
|
||||
#define M_CLASS_INSN(namea, nameb, opcode, level) \
|
||||
{ namea "_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
|
||||
{ namea "_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
|
||||
{ namea "_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
|
||||
{ namea "_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
|
||||
{ nameb "_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
|
||||
{ nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
|
||||
{ nameb "_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }
|
||||
{ namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
|
||||
{ namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
|
||||
{ namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
|
||||
{ namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
|
||||
{ namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
|
||||
{ nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
|
||||
{ nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
|
||||
{ nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
|
||||
{ nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
|
||||
{ nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
|
||||
|
||||
/* P: General 2-operand operation with parallell store
|
||||
Syntax: <ia> src2, dst1 || <ib> src3, dst2
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
|
|
@ -532,13 +625,13 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
Alias: a||b, b||a
|
||||
*/
|
||||
#define P_CLASS_INSN(namea, nameb, opcode, level) \
|
||||
{ namea "_" nameb, opcode, 0xfe000000, "I,L|H,J", level }, \
|
||||
{ nameb "_" namea, opcode, 0xfe000000, "H,J|I,L", level }
|
||||
{ namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
|
||||
{ nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
|
||||
|
||||
/* Q: General 3-operand operation with parallell store
|
||||
Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
|
|
@ -546,16 +639,16 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
Alias: a||b, b||a, a3||b, b||a3
|
||||
*/
|
||||
#define Q_CLASS_INSN(namea, nameb, opcode, level) \
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
|
||||
|
||||
/* QC: General commutative 3-operand operation with parallell store
|
||||
Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
|
||||
<ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
|
|
@ -564,14 +657,14 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
Alias: a||b, b||a, a3||b, b||a3
|
||||
*/
|
||||
#define QC_CLASS_INSN(namea, nameb, opcode, level) \
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|I,K;L", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|I,K;L", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
|
||||
{ namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \
|
||||
{ nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
|
||||
{ namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
|
||||
{ nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
|
||||
|
||||
/* R: General register integer operation
|
||||
Syntax: <i> dst
|
||||
|
|
@ -781,7 +874,7 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
|
||||
|
||||
/* Define c3x opcodes for assembler and disassembler. */
|
||||
static const c4x_inst_t c3x_insts[] =
|
||||
static const c4x_inst_t c4x_insts[] =
|
||||
{
|
||||
/* Put synonyms after the desired forms in table so that they get
|
||||
overwritten in the lookup table. The disassembler will thus
|
||||
|
|
@ -792,298 +885,195 @@ static const c4x_inst_t c3x_insts[] =
|
|||
the sti1||sti2 form is used. We also allow sti2||sti1
|
||||
which is equivalent to the default sti||sti form.
|
||||
*/
|
||||
B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
|
||||
P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
|
||||
A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
|
||||
P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
|
||||
A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
|
||||
B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
|
||||
SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
|
||||
A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
|
||||
T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
|
||||
A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
|
||||
T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
|
||||
Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
|
||||
J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
|
||||
J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
|
||||
{ "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
|
||||
{ "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
|
||||
B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
|
||||
S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
|
||||
A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
|
||||
T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
|
||||
D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
|
||||
D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
|
||||
AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
|
||||
P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
|
||||
BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
|
||||
P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
|
||||
{ "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
|
||||
{ "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
|
||||
{ "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE }, /* Z_CLASS */
|
||||
B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
|
||||
B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
|
||||
LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
|
||||
P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
|
||||
BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
|
||||
B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
|
||||
A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
|
||||
LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
|
||||
P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
|
||||
AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
|
||||
A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
|
||||
{ "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
|
||||
B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
|
||||
{ "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
|
||||
T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
|
||||
Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
|
||||
{ "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
|
||||
B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
|
||||
SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
|
||||
A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
|
||||
A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
|
||||
B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
|
||||
P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
|
||||
A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
|
||||
P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
|
||||
A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
|
||||
B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
|
||||
P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
|
||||
R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
|
||||
RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
|
||||
R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
|
||||
RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
|
||||
{ "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
|
||||
{ "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
|
||||
B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
|
||||
R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
|
||||
R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
|
||||
R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
|
||||
R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
|
||||
{ "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
|
||||
{ "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
|
||||
A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
|
||||
{ "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
|
||||
B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
|
||||
LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
|
||||
B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
|
||||
A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
|
||||
{ "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
|
||||
{ "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
|
||||
LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
|
||||
A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
|
||||
A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
|
||||
T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
|
||||
B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
|
||||
S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
|
||||
Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
|
||||
T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
|
||||
Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
|
||||
B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
|
||||
{ "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
|
||||
{ "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
|
||||
AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
|
||||
T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
|
||||
AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
|
||||
|
||||
B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
|
||||
P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
|
||||
A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
|
||||
P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
|
||||
A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
|
||||
B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
|
||||
SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
|
||||
A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
|
||||
T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
|
||||
A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
|
||||
T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
|
||||
Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
|
||||
J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
|
||||
J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
|
||||
J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
|
||||
J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
|
||||
{ "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
|
||||
{ "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
|
||||
{ "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
|
||||
B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
|
||||
S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
|
||||
A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
|
||||
T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
|
||||
D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
|
||||
D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
|
||||
AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
|
||||
P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
|
||||
BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
|
||||
P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
|
||||
B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
|
||||
P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
|
||||
{ "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
|
||||
{ "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
|
||||
{ "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */
|
||||
{ "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
|
||||
{ "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
|
||||
{ "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
|
||||
{ "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
|
||||
AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
|
||||
B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
|
||||
{ "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
|
||||
B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
|
||||
LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
|
||||
P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
|
||||
BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
|
||||
B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
|
||||
{ "ldhi", 0x1fe00000, 0xffe00000, "U,r" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldhi", 0x1fe00000, 0xffe00000, "#,r" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
|
||||
LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
|
||||
P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
|
||||
AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
|
||||
A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
|
||||
{ "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
|
||||
B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
|
||||
{ "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
|
||||
{ "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
|
||||
T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
|
||||
Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
|
||||
A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
|
||||
{ "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
|
||||
B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
|
||||
SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
|
||||
A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
|
||||
M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
|
||||
A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
|
||||
TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
|
||||
TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
|
||||
A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
|
||||
B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
|
||||
P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
|
||||
A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
|
||||
P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
|
||||
A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
|
||||
B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
|
||||
P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
|
||||
AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
|
||||
TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
|
||||
QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
|
||||
R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
|
||||
RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
|
||||
R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
|
||||
RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
|
||||
BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
|
||||
{ "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
|
||||
{ "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
|
||||
{ "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
|
||||
{ "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
{ "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
|
||||
B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
|
||||
R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
|
||||
R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
|
||||
R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
|
||||
R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
|
||||
{ "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
|
||||
{ "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
|
||||
{ "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
|
||||
{ "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
|
||||
A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
|
||||
B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
|
||||
{ "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
|
||||
A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
|
||||
B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
|
||||
LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
|
||||
B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
|
||||
A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
|
||||
{ "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
|
||||
{ "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
|
||||
LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
|
||||
A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
|
||||
{ "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
|
||||
{ "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
|
||||
T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
|
||||
B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
|
||||
S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
|
||||
Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
|
||||
T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
|
||||
Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
|
||||
B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
|
||||
A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
|
||||
{ "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
|
||||
B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
|
||||
P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
|
||||
{ "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
|
||||
{ "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
|
||||
AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
|
||||
T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
|
||||
AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
|
||||
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
|
||||
|
||||
/* Dummy entry, not included in c3x_num_insts. This
|
||||
lets code examine entry i + 1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0, 0x00, "", 0 }
|
||||
};
|
||||
|
||||
const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1);
|
||||
|
||||
/* Define c4x additional opcodes for assembler and disassembler. */
|
||||
static const c4x_inst_t c4x_insts[] =
|
||||
{
|
||||
J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
|
||||
J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
|
||||
B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
|
||||
P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
|
||||
{ "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
|
||||
{ "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
|
||||
{ "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
|
||||
{ "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
|
||||
AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
|
||||
{ "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldhi", 0x1fe00000, 0xffe00000, "U,r" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldhi", 0x1fe00000, 0xffe00000, "#,r" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
|
||||
{ "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
|
||||
A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
|
||||
AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
|
||||
A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
|
||||
A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
|
||||
TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
|
||||
A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
|
||||
TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
|
||||
BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
|
||||
{ "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
|
||||
{ "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
|
||||
{ "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
|
||||
{ "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
|
||||
B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
|
||||
{ "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
|
||||
{ "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
|
||||
B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
|
||||
P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
|
||||
|
||||
/* Dummy entry, not included in num_insts. This
|
||||
lets code examine entry i+1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0, 0x00, "", 0 }
|
||||
};
|
||||
|
||||
const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
|
||||
|
||||
|
||||
struct c4x_cond
|
||||
{
|
||||
char * name;
|
||||
unsigned long cond;
|
||||
};
|
||||
|
||||
typedef struct c4x_cond c4x_cond_t;
|
||||
|
||||
/* Define conditional branch/load suffixes. Put desired form for
|
||||
disassembler last. */
|
||||
static const c4x_cond_t c4x_conds[] =
|
||||
{
|
||||
{ "u", 0x00 },
|
||||
{ "c", 0x01 }, { "lo", 0x01 },
|
||||
{ "ls", 0x02 },
|
||||
{ "hi", 0x03 },
|
||||
{ "nc", 0x04 }, { "hs", 0x04 },
|
||||
{ "z", 0x05 }, { "eq", 0x05 },
|
||||
{ "nz", 0x06 }, { "ne", 0x06 },
|
||||
{ "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
|
||||
{ "le", 0x08 },
|
||||
{ "p", 0x09 }, { "gt", 0x09 },
|
||||
{ "nn", 0x0a }, { "ge", 0x0a },
|
||||
{ "nv", 0x0c },
|
||||
{ "v", 0x0d },
|
||||
{ "nuf", 0x0e },
|
||||
{ "uf", 0x0f },
|
||||
{ "nlv", 0x10 },
|
||||
{ "lv", 0x11 },
|
||||
{ "nluf", 0x12 },
|
||||
{ "luf", 0x13 },
|
||||
{ "zuf", 0x14 },
|
||||
/* Dummy entry, not included in num_conds. This
|
||||
lets code examine entry i+1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0}
|
||||
};
|
||||
|
||||
const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
|
||||
|
||||
struct c4x_indirect
|
||||
{
|
||||
char * name;
|
||||
unsigned long modn;
|
||||
};
|
||||
|
||||
typedef struct c4x_indirect c4x_indirect_t;
|
||||
|
||||
/* Define indirect addressing modes where:
|
||||
d displacement (signed)
|
||||
y ir0
|
||||
z ir1 */
|
||||
|
||||
static const c4x_indirect_t c4x_indirects[] =
|
||||
{
|
||||
{ "*+a(d)", 0x00 },
|
||||
{ "*-a(d)", 0x01 },
|
||||
{ "*++a(d)", 0x02 },
|
||||
{ "*--a(d)", 0x03 },
|
||||
{ "*a++(d)", 0x04 },
|
||||
{ "*a--(d)", 0x05 },
|
||||
{ "*a++(d)%", 0x06 },
|
||||
{ "*a--(d)%", 0x07 },
|
||||
{ "*+a(y)", 0x08 },
|
||||
{ "*-a(y)", 0x09 },
|
||||
{ "*++a(y)", 0x0a },
|
||||
{ "*--a(y)", 0x0b },
|
||||
{ "*a++(y)", 0x0c },
|
||||
{ "*a--(y)", 0x0d },
|
||||
{ "*a++(y)%", 0x0e },
|
||||
{ "*a--(y)%", 0x0f },
|
||||
{ "*+a(z)", 0x10 },
|
||||
{ "*-a(z)", 0x11 },
|
||||
{ "*++a(z)", 0x12 },
|
||||
{ "*--a(z)", 0x13 },
|
||||
{ "*a++(z)", 0x14 },
|
||||
{ "*a--(z)", 0x15 },
|
||||
{ "*a++(z)%", 0x16 },
|
||||
{ "*a--(z)%", 0x17 },
|
||||
{ "*a", 0x18 },
|
||||
{ "*a++(y)b", 0x19 },
|
||||
/* Dummy entry, not included in num_indirects. This
|
||||
lets code examine entry i+1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0}
|
||||
};
|
||||
|
||||
#define C3X_MODN_MAX 0x19
|
||||
|
||||
const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
|
||||
|
||||
* tic4x-dis.c: Added support for enhanced and special insn.
|
||||
(c4x_print_op): Added insn class 'i' and 'j'
|
||||
(c4x_hash_opcode_special): Add to support special insn
|
||||
(c4x_hash_opcode): Update to support the new opcode-list
|
||||
format. Add support for the new special insns.
|
||||
(c4x_disassemble): New opcode-list support.
|
||||
|
||||
2002-11-16 Klee Dienes <kdienes@apple.com>
|
||||
|
||||
* m88k-dis.c: Include libiberty.h (for xmalloc).
|
||||
|
|
|
|||
|
|
@ -25,7 +25,8 @@
|
|||
|
||||
#define C4X_DEBUG 0
|
||||
|
||||
#define C4X_HASH_SIZE 11 /* 11 and above should give unique entries. */
|
||||
#define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
|
||||
#define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
|
|
@ -50,35 +51,37 @@ static int c4x_version = 0;
|
|||
static int c4x_dp = 0;
|
||||
|
||||
static int c4x_pc_offset
|
||||
PARAMS ((unsigned int));
|
||||
PARAMS ((unsigned int));
|
||||
static int c4x_print_char
|
||||
PARAMS ((struct disassemble_info *, char));
|
||||
PARAMS ((struct disassemble_info *, char));
|
||||
static int c4x_print_str
|
||||
PARAMS ((struct disassemble_info *, char *));
|
||||
PARAMS ((struct disassemble_info *, char *));
|
||||
static int c4x_print_register
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_addr
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_relative
|
||||
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
|
||||
void c4x_print_ftoa
|
||||
PARAMS ((unsigned int, FILE *, fprintf_ftype));
|
||||
PARAMS ((unsigned int, FILE *, fprintf_ftype));
|
||||
static int c4x_print_direct
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_immed
|
||||
PARAMS ((struct disassemble_info *, immed_t, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, immed_t, unsigned long));
|
||||
static int c4x_print_cond
|
||||
PARAMS ((struct disassemble_info *, unsigned int));
|
||||
PARAMS ((struct disassemble_info *, unsigned int));
|
||||
static int c4x_print_indirect
|
||||
PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
|
||||
static int c4x_print_op
|
||||
PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
|
||||
PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
|
||||
static void c4x_hash_opcode_special
|
||||
PARAMS ((c4x_inst_t **, const c4x_inst_t *));
|
||||
static void c4x_hash_opcode
|
||||
PARAMS ((c4x_inst_t **, const c4x_inst_t *));
|
||||
PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long));
|
||||
static int c4x_disassemble
|
||||
PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
|
||||
PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
|
||||
int print_insn_tic4x
|
||||
PARAMS ((bfd_vma, struct disassemble_info *));
|
||||
PARAMS ((bfd_vma, struct disassemble_info *));
|
||||
|
||||
|
||||
static int
|
||||
|
|
@ -489,12 +492,29 @@ c4x_print_op (info, instruction, p, pc)
|
|||
EXTRU (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case 'i': /* Extended indirect 0--7 */
|
||||
if ( EXTRU (instruction, 7, 5) == 7 )
|
||||
{
|
||||
if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) )
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
/* Fallthrough */
|
||||
|
||||
case 'I': /* indirect (short) 0--7 */
|
||||
if (! c4x_print_indirect (info, INDIRECT_SHORT,
|
||||
EXTRU (instruction, 7, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'j': /* Extended indirect 8--15 */
|
||||
if ( EXTRU (instruction, 15, 13) == 7 )
|
||||
{
|
||||
if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) )
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case 'J': /* indirect (short) 8--15 */
|
||||
if (! c4x_print_indirect (info, INDIRECT_SHORT,
|
||||
EXTRU (instruction, 15, 8)))
|
||||
|
|
@ -629,9 +649,43 @@ c4x_print_op (info, instruction, p, pc)
|
|||
}
|
||||
|
||||
static void
|
||||
c4x_hash_opcode (optable, inst)
|
||||
c4x_inst_t **optable;
|
||||
c4x_hash_opcode_special (optable_special, inst)
|
||||
c4x_inst_t **optable_special;
|
||||
const c4x_inst_t *inst;
|
||||
{
|
||||
int i;
|
||||
|
||||
for( i=0; i<C4X_SPESOP_SIZE; i++ )
|
||||
if( optable_special[i] != NULL
|
||||
&& optable_special[i]->opcode == inst->opcode )
|
||||
{
|
||||
/* Collision (we have it already) - overwrite */
|
||||
optable_special[i] = (void *)inst;
|
||||
return;
|
||||
}
|
||||
|
||||
for( i=0; i<C4X_SPESOP_SIZE; i++ )
|
||||
if( optable_special[i] == NULL )
|
||||
{
|
||||
/* Add the new opcode */
|
||||
optable_special[i] = (void *)inst;
|
||||
return;
|
||||
}
|
||||
|
||||
/* This should never occur. This happens if the number of special
|
||||
instructions exceeds C4X_SPESOP_SIZE. Please increase the variable
|
||||
of this variable */
|
||||
#if C4X_DEBUG
|
||||
printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
|
||||
c4x_inst_t **optable;
|
||||
c4x_inst_t **optable_special;
|
||||
const c4x_inst_t *inst;
|
||||
const unsigned long c4x_oplevel;
|
||||
{
|
||||
int j;
|
||||
int opcode = inst->opcode >> (32 - C4X_HASH_SIZE);
|
||||
|
|
@ -641,7 +695,8 @@ c4x_hash_opcode (optable, inst)
|
|||
have unique entries so there's no point having a linked list
|
||||
for each entry? */
|
||||
for (j = opcode; j < opmask; j++)
|
||||
if ((j & opmask) == opcode)
|
||||
if ( (j & opmask) == opcode
|
||||
&& inst->oplevel & c4x_oplevel )
|
||||
{
|
||||
#if C4X_DEBUG
|
||||
/* We should only have collisions for synonyms like
|
||||
|
|
@ -650,7 +705,21 @@ c4x_hash_opcode (optable, inst)
|
|||
printf("Collision at index %d, %s and %s\n",
|
||||
j, optable[j]->name, inst->name);
|
||||
#endif
|
||||
optable[j] = (void *)inst;
|
||||
/* Catch those ops that collide with others already inside the
|
||||
hash, and have a opmask greater than the one we use in the
|
||||
hash. Store them in a special-list, that will handle full
|
||||
32-bit INSN, not only the first 11-bit (or so). */
|
||||
if ( optable[j] != NULL
|
||||
&& inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) )
|
||||
{
|
||||
/* Add the instruction already on the list */
|
||||
c4x_hash_opcode_special(optable_special, optable[j]);
|
||||
|
||||
/* Add the new instruction */
|
||||
c4x_hash_opcode_special(optable_special, inst);
|
||||
}
|
||||
|
||||
optable[j] = (void *)inst;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -667,36 +736,63 @@ c4x_disassemble (pc, instruction, info)
|
|||
struct disassemble_info *info;
|
||||
{
|
||||
static c4x_inst_t **optable = NULL;
|
||||
static c4x_inst_t **optable_special = NULL;
|
||||
c4x_inst_t *p;
|
||||
int i;
|
||||
unsigned long c4x_oplevel;
|
||||
|
||||
c4x_version = info->mach;
|
||||
|
||||
c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0;
|
||||
c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
|
||||
|
||||
if (optable == NULL)
|
||||
{
|
||||
optable = (c4x_inst_t **)
|
||||
xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE));
|
||||
|
||||
optable_special = (c4x_inst_t **)
|
||||
xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE );
|
||||
|
||||
/* Install opcodes in reverse order so that preferred
|
||||
forms overwrite synonyms. */
|
||||
for (i = c3x_num_insts - 1; i >= 0; i--)
|
||||
c4x_hash_opcode (optable, &c3x_insts[i]);
|
||||
if (IS_CPU_C4X (c4x_version))
|
||||
{
|
||||
for (i = c4x_num_insts - 1; i >= 0; i--)
|
||||
c4x_hash_opcode (optable, &c4x_insts[i]);
|
||||
}
|
||||
for (i = c4x_num_insts - 1; i >= 0; i--)
|
||||
c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel);
|
||||
|
||||
/* We now need to remove the insn that are special from the
|
||||
"normal" optable, to make the disasm search this extra list
|
||||
for them.
|
||||
*/
|
||||
for (i=0; i<C4X_SPESOP_SIZE; i++)
|
||||
if ( optable_special[i] != NULL )
|
||||
optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL;
|
||||
}
|
||||
|
||||
/* See if we can pick up any loading of the DP register... */
|
||||
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
|
||||
c4x_dp = EXTRU (instruction, 15, 0);
|
||||
|
||||
|
||||
p = optable[instruction >> (32 - C4X_HASH_SIZE)];
|
||||
if (p != NULL && ((instruction & p->opmask) == p->opcode)
|
||||
&& c4x_print_op (NULL, instruction, p, pc))
|
||||
c4x_print_op (info, instruction, p, pc);
|
||||
if ( p != NULL )
|
||||
{
|
||||
if ( ((instruction & p->opmask) == p->opcode)
|
||||
&& c4x_print_op (NULL, instruction, p, pc) )
|
||||
c4x_print_op (info, instruction, p, pc);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
||||
{
|
||||
for (i = 0; i<C4X_SPESOP_SIZE; i++)
|
||||
if (optable_special[i] != NULL
|
||||
&& optable_special[i]->opcode == instruction )
|
||||
{
|
||||
(*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
|
||||
break;
|
||||
}
|
||||
if (i==C4X_SPESOP_SIZE)
|
||||
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
||||
}
|
||||
|
||||
/* Return size of insn in words. */
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue