binutils/
2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * doc/binutils.texi: Document the new intel-mnemonic and intel-mnemonic options for i386 disassembler. gas/testsuite/ 2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/compat-intel.d: New file. * gas/i386/compat.d: Likewise. * gas/i386/compat.s: Likewise. * gas/i386/i386.exp: Run compat. opcodes/ 2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (intel_mnemonic): New. (print_i386_disassembler_options): Display att-mnemonic and intel-mnemonic options. (print_insn): Handle att-mnemonic and intel-mnemonic. (float_reg): Replace SYSV386_COMPAT with "!M" and "M". (putop): Handle "!M" and "M".
This commit is contained in:
H.J. Lu
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@ -1,3 +1,8 @@
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2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
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* doc/binutils.texi: Document the new intel-mnemonic and
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intel-mnemonic options for i386 disassembler.
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2007-12-07 Bob Wilson <bob.wilson@acm.org>
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* readelf.c (is_32bit_pcrel_reloc): Add Xtensa.
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@ -1801,7 +1801,11 @@ switch, but allow finer grained control. Multiple selections from the
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following may be specified as a comma separated string.
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@option{x86-64}, @option{i386} and @option{i8086} select disassembly for
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the given architecture. @option{intel} and @option{att} select between
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intel syntax mode and AT&T syntax mode. @option{addr64}, @option{addr32},
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intel syntax mode and AT&T syntax mode.
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@option{intel-mnemonic} and @option{att-mnemonic} select between
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intel mnemonic mode and AT&T mnemonic mode. @option{intel-mnemonic}
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implies @option{intel} and @option{att-mnemonic} implies @option{att}.
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@option{addr64}, @option{addr32},
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@option{addr16}, @option{data32} and @option{data16} specify the default
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address size and operand size. These four options will be overridden if
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@option{x86-64}, @option{i386} or @option{i8086} appear later in the
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@ -1,3 +1,11 @@
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2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/compat-intel.d: New file.
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* gas/i386/compat.d: Likewise.
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* gas/i386/compat.s: Likewise.
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* gas/i386/i386.exp: Run compat.
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2007-12-13 Bob Wilson <bob.wilson@acm.org>
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* gas/xtensa/all.exp: Run new weak-call test.
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@ -6,9 +14,9 @@
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2007-12-11 Catherine Moore <clm@codesourcery.com>
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gas/elf/symtab.s: New test.
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gas/elf/symtab.d: New expected output.
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gas/elf/elf.exp: Run the new symbtab test.
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* gas/elf/symtab.s: New test.
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* gas/elf/symtab.d: New expected output.
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* gas/elf/elf.exp: Run the new symbtab test.
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2007-12-10 Richard Sandiford <rsandifo@nildram.co.uk>
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26
gas/testsuite/gas/i386/compat-intel.d
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26
gas/testsuite/gas/i386/compat-intel.d
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@ -0,0 +1,26 @@
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#objdump: -d -Mintel-mnemonic
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#name: i386 float Intel mnemonic
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#source: compat.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: dc e3 fsubr st\(3\),st
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[ ]*[a-f0-9]+: de e1 fsubrp st\(1\),st
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[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
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[ ]*[a-f0-9]+: de e3 fsubrp st\(3\),st
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[ ]*[a-f0-9]+: dc eb fsub st\(3\),st
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[ ]*[a-f0-9]+: de e9 fsubp st\(1\),st
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[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
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[ ]*[a-f0-9]+: de eb fsubp st\(3\),st
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[ ]*[a-f0-9]+: dc f3 fdivr st\(3\),st
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[ ]*[a-f0-9]+: de f1 fdivrp st\(1\),st
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[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
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[ ]*[a-f0-9]+: de f3 fdivrp st\(3\),st
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[ ]*[a-f0-9]+: dc fb fdiv st\(3\),st
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[ ]*[a-f0-9]+: de f9 fdivp st\(1\),st
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[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
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[ ]*[a-f0-9]+: de fb fdivp st\(3\),st
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#pass
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25
gas/testsuite/gas/i386/compat.d
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25
gas/testsuite/gas/i386/compat.d
Normal file
@ -0,0 +1,25 @@
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#objdump: -d -Matt-mnemonic
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#name: i386 float AT&T mnemonic
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: dc e3 fsub %st,%st\(3\)
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[ ]*[a-f0-9]+: de e1 fsubp %st,%st\(1\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: dc eb fsubr %st,%st\(3\)
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[ ]*[a-f0-9]+: de e9 fsubrp %st,%st\(1\)
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[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
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[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
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[ ]*[a-f0-9]+: dc f3 fdiv %st,%st\(3\)
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[ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
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[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
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[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
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[ ]*[a-f0-9]+: dc fb fdivr %st,%st\(3\)
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[ ]*[a-f0-9]+: de f9 fdivrp %st,%st\(1\)
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[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
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[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
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#pass
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18
gas/testsuite/gas/i386/compat.s
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18
gas/testsuite/gas/i386/compat.s
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@ -0,0 +1,18 @@
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# Check SYSV mnemonic instructions.
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.text
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fsub %st,%st(3)
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fsubp
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fsubp %st(3)
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fsubp %st,%st(3)
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fsubr %st,%st(3)
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fsubrp
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fsubrp %st(3)
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fsubrp %st,%st(3)
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fdiv %st,%st(3)
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fdivp
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fdivp %st(3)
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fdivp %st,%st(3)
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fdivr %st,%st(3)
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fdivrp
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fdivrp %st(3)
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fdivrp %st,%st(3)
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@ -96,6 +96,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "reg"
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run_dump_test "reg-intel"
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run_dump_test "i386"
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run_dump_test "compat"
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run_dump_test "compat-intel"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -1,3 +1,12 @@
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2007-12-22 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (intel_mnemonic): New.
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(print_i386_disassembler_options): Display att-mnemonic and
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intel-mnemonic options.
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(print_insn): Handle att-mnemonic and intel-mnemonic.
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(float_reg): Replace SYSV386_COMPAT with "!M" and "M".
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(putop): Handle "!M" and "M".
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2007-12-21 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.am (i386-gen.o): Also depend on
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@ -730,6 +730,7 @@ struct dis386 {
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'J' => print 'l'
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'K' => print 'd' or 'q' if rex prefix is present.
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'L' => print 'l' if suffix_always is true
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'M' => print 'r' if intel_mnemonic is false.
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'N' => print 'n' if instruction has no wait "prefix"
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'O' => print 'd' or 'o' (or 'q' in Intel mode)
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'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
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@ -746,6 +747,7 @@ struct dis386 {
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'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
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suffix_always is true.
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'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
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'!' => change condition from true to false or from false to true.
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Many of the above letters print nothing in Intel mode. See "putop"
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for the details.
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@ -5058,6 +5060,7 @@ static bfd_vma start_pc;
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*/
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static char intel_syntax;
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static char intel_mnemonic = !SYSV386_COMPAT;
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static char open_char;
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static char close_char;
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static char separator_char;
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@ -5102,6 +5105,10 @@ with the -M switch (multiple options should be separated by commas):\n"));
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fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
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fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
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fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
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fprintf (stream, _(" att-mnemonic\n"
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" Display instruction in AT&T mnemonic\n"));
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fprintf (stream, _(" intel-mnemonic\n"
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" Display instruction in Intel mnemonic\n"));
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fprintf (stream, _(" addr64 Assume 64bit address size\n"));
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fprintf (stream, _(" addr32 Assume 32bit address size\n"));
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fprintf (stream, _(" addr16 Assume 16bit address size\n"));
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@ -5245,10 +5252,14 @@ print_insn (bfd_vma pc, disassemble_info *info)
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else if (CONST_STRNEQ (p, "intel"))
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{
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intel_syntax = 1;
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if (CONST_STRNEQ (p + 5, "-mnemonic"))
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intel_mnemonic = 1;
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}
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else if (CONST_STRNEQ (p, "att"))
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{
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intel_syntax = 0;
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if (CONST_STRNEQ (p + 3, "-mnemonic"))
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intel_mnemonic = 0;
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}
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else if (CONST_STRNEQ (p, "addr"))
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{
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@ -5790,17 +5801,10 @@ static const struct dis386 float_reg[][8] = {
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{ "fmul", { STi, ST } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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#if SYSV386_COMPAT
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{ "fsub", { STi, ST } },
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{ "fsubr", { STi, ST } },
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{ "fdiv", { STi, ST } },
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{ "fdivr", { STi, ST } },
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#else
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{ "fsubr", { STi, ST } },
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{ "fsub", { STi, ST } },
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{ "fdivr", { STi, ST } },
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{ "fdiv", { STi, ST } },
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#endif
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{ "fsub!M", { STi, ST } },
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{ "fsubM", { STi, ST } },
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{ "fdiv!M", { STi, ST } },
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{ "fdivM", { STi, ST } },
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},
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/* dd */
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{
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@ -5819,17 +5823,10 @@ static const struct dis386 float_reg[][8] = {
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{ "fmulp", { STi, ST } },
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{ "(bad)", { XX } },
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{ FGRPde_3 },
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#if SYSV386_COMPAT
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{ "fsubp", { STi, ST } },
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{ "fsubrp", { STi, ST } },
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{ "fdivp", { STi, ST } },
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{ "fdivrp", { STi, ST } },
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#else
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{ "fsubrp", { STi, ST } },
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{ "fsubp", { STi, ST } },
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{ "fdivrp", { STi, ST } },
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{ "fdivp", { STi, ST } },
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#endif
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{ "fsub!Mp", { STi, ST } },
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{ "fsubMp", { STi, ST } },
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{ "fdiv!Mp", { STi, ST } },
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{ "fdivMp", { STi, ST } },
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},
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/* df */
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{
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@ -5967,6 +5964,7 @@ putop (const char *template, int sizeflag)
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{
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const char *p;
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int alt = 0;
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int cond = 1;
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for (p = template; *p; p++)
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{
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@ -5975,6 +5973,9 @@ putop (const char *template, int sizeflag)
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default:
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*obufp++ = *p;
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break;
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case '!':
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cond = 0;
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break;
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case '{':
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alt = 0;
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if (intel_syntax)
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@ -6114,6 +6115,10 @@ putop (const char *template, int sizeflag)
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if (sizeflag & SUFFIX_ALWAYS)
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*obufp++ = 'l';
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break;
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case 'M':
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if (intel_mnemonic != cond)
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*obufp++ = 'r';
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break;
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case 'N':
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if ((prefixes & PREFIX_FWAIT) == 0)
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*obufp++ = 'n';
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