x86: fix swapped operand handling for BNDMOV
The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
d6793fa1ac
commit
9f79e88693
@ -1,3 +1,10 @@
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2018-03-22 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/opts.s: Add bndmov cases.
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* testsuite/gas/i386/opts.d, testsuite/gas/i386/opts-intel.d,
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testsuite/gas/i386/sse2avx-opts.d,
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testsuite/gas/i386/sse2avx-opts-intel.d: Adjust expectations.
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2018-03-22 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_mem_size): Extend sub-xmmword
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@ -166,6 +166,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
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[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
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[ ]*[a-f0-9]+: 00 d1 add cl,dl
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[ ]*[a-f0-9]+: 02 ca add.s cl,dl
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[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
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@ -270,4 +272,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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[ ]*[a-f0-9]+: 66 0f 1a ca bndmov bnd1,bnd2
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[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s bnd1,bnd2
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#pass
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@ -165,6 +165,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
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[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
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[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
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[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
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[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
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[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
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@ -269,4 +271,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
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[ ]*[a-f0-9]+: 66 0f 1a ca bndmov %bnd2,%bnd1
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[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s %bnd2,%bnd1
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#pass
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@ -172,6 +172,10 @@ _start:
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movq %mm0,%mm4
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movq.s %mm0,%mm4
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# Tests for op bnd, bnd
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bndmov %bnd1,%bnd2
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bndmov.s %bnd1,%bnd2
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.intel_syntax noprefix
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# Tests for op reg, reg
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@ -287,3 +291,7 @@ _start:
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# Tests for op mm, mm
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movq mm4,mm0
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movq.s mm4,mm0
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# Tests for op bnd, bnd
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bndmov bnd1,bnd2
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bndmov.s bnd1,bnd2
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@ -167,6 +167,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov bnd2,bnd1
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[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s bnd2,bnd1
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[ ]*[a-f0-9]+: 00 d1 add cl,dl
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[ ]*[a-f0-9]+: 02 ca add.s cl,dl
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[ ]*[a-f0-9]+: 66 01 d1 add cx,dx
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@ -271,4 +273,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s xmm2,xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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[ ]*[a-f0-9]+: 66 0f 1a ca bndmov bnd1,bnd2
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[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s bnd1,bnd2
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#pass
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@ -167,6 +167,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
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[ ]*[a-f0-9]+: 66 0f 1a d1 bndmov %bnd1,%bnd2
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[ ]*[a-f0-9]+: 66 0f 1b ca bndmov.s %bnd1,%bnd2
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[ ]*[a-f0-9]+: 00 d1 addb %dl,%cl
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[ ]*[a-f0-9]+: 02 ca addb.s %dl,%cl
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[ ]*[a-f0-9]+: 66 01 d1 addw %dx,%cx
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@ -271,4 +273,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 ca 11 e2 vmovss.s %xmm4,%xmm6,%xmm2
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[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
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[ ]*[a-f0-9]+: 66 0f 1a ca bndmov %bnd2,%bnd1
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[ ]*[a-f0-9]+: 66 0f 1b d1 bndmov.s %bnd2,%bnd1
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#pass
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@ -1,3 +1,11 @@
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2018-03-22 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (EbndS, bnd_swap_mode): New.
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(prefix_table): Use EbndS.
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(OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
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* i386-opc.tbl (bndmov): Move misplaced Load.
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* i386-tlb.h: Re-generate.
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2018-03-22 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
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@ -248,6 +248,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Eb { OP_E, b_mode }
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#define Ebnd { OP_E, bnd_mode }
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#define EbS { OP_E, b_swap_mode }
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#define EbndS { OP_E, bnd_swap_mode }
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#define Ev { OP_E, v_mode }
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#define Ev_bnd { OP_E, v_bnd_mode }
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#define EvS { OP_E, v_swap_mode }
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@ -560,7 +561,10 @@ enum
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dq_mode,
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/* registers like dq_mode, memory like w_mode. */
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dqw_mode,
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/* bounds operand */
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bnd_mode,
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/* bounds operand with operand swapped */
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bnd_swap_mode,
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/* 4- or 6-byte pointer operand */
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f_mode,
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const_1_mode,
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@ -3890,7 +3894,7 @@ static const struct dis386 prefix_table[][4] = {
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{
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{ MOD_TABLE (MOD_0F1B_PREFIX_0) },
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{ MOD_TABLE (MOD_0F1B_PREFIX_1) },
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{ "bndmov", { Ebnd, Gbnd }, 0 },
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{ "bndmov", { EbndS, Gbnd }, 0 },
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{ "bndcn", { Gbnd, Ev_bnd }, 0 },
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},
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@ -15047,6 +15051,7 @@ OP_E_register (int bytemode, int sizeflag)
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if ((sizeflag & SUFFIX_ALWAYS)
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&& (bytemode == b_swap_mode
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|| bytemode == bnd_swap_mode
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|| bytemode == v_swap_mode))
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swap_operand ();
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@ -15076,6 +15081,7 @@ OP_E_register (int bytemode, int sizeflag)
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names = address_mode == mode_64bit ? names64 : names32;
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break;
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case bnd_mode:
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case bnd_swap_mode:
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if (reg > 0x3)
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{
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oappend ("(bad)");
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@ -15272,7 +15278,8 @@ OP_E_memory (int bytemode, int sizeflag)
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int scale = 0;
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int addr32flag = !((sizeflag & AFLAG)
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|| bytemode == v_bnd_mode
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|| bytemode == bnd_mode);
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|| bytemode == bnd_mode
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|| bytemode == bnd_swap_mode);
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const char **indexes64 = names64;
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const char **indexes32 = names32;
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@ -15389,7 +15396,8 @@ OP_E_memory (int bytemode, int sizeflag)
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if ((havebase || haveindex || riprel)
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&& (bytemode != v_bnd_mode)
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&& (bytemode != bnd_mode))
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&& (bytemode != bnd_mode)
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&& (bytemode != bnd_swap_mode))
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used_prefixes |= PREFIX_ADDR;
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if (havedisp || (intel_syntax && riprel))
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@ -2872,8 +2872,8 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|
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// MPX instructions.
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bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex, RegBND }
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bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
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bndmov, 2, 0x660f1b, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND }
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bndmov, 2, 0x660f1a, None, 2, CpuMPX, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
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bndmov, 2, 0x660f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|RegBND }
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bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
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bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex, RegBND }
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bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex, RegBND }
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@ -69914,7 +69914,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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@ -69931,7 +69931,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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