x86: add missing IgnoreSize
For proper code generation in 16-bit mode (or to avoid the "same type of prefix used twice" diagnostic there), IgnoreSize is needed on certain templates allowing for just 32-(and maybe 64-)bit operands. Beyond adding tests for the previously broken cases, also add ones for the previously working cases where IgnoreSize is needed for the same reason (leaving out MPX for now, as that'll require an assembler change first). Some minor adjustments to tests get done such that re-use of the same code for 16-bit code generation testing becomes easier.
This commit is contained in:
parent
b630c145c0
commit
a04973848d
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@ -1,3 +1,24 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
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testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
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testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
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testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
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* testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
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as well as a BSWAP one.
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* testsuite/gas/i386/rdpid.s: Add 16-bit case.
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* testsuite/gas/i386/sse2-16bit.s: Cover more insns.
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* testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
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testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
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testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
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testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
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testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
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testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
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testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
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testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
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testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
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testsuite/gas/i386/vmx.d: Adjust expectations.
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
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@ -20,12 +20,22 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox ecx,edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 82 8f 01 00 00 adcx eax,DWORD PTR \[edx\+0x18f\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 42 24 adcx eax,DWORD PTR \[edx\+0x24\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx edx,ecx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 c0 1d fe ff adcx edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 54 f4 f4 adcx edx,DWORD PTR \[esp\+esi\*8-0xc\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 82 8f 01 00 00 adox eax,DWORD PTR \[edx\+0x18f\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 42 24 adox eax,DWORD PTR \[edx\+0x24\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox edx,ecx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 c0 1d fe ff adox edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 54 f4 f4 adox edx,DWORD PTR \[esp\+esi\*8-0xc\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox eax,DWORD PTR \[eax\]
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 42 24 adcx eax,DWORD PTR \[bp\+si\+0x24\]
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx edx,ecx
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 54 f4 adcx edx,DWORD PTR \[si-0xc\]
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[ ]*[a-f0-9]+: f4 hlt *
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx eax,DWORD PTR \[bx\+si\]
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 42 24 adox eax,DWORD PTR \[bp\+si\+0x24\]
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox edx,ecx
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 54 f4 adox edx,DWORD PTR \[si-0xc\]
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[ ]*[a-f0-9]+: f4 hlt *
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox eax,DWORD PTR \[bx\+si\]
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#pass
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@ -19,12 +19,22 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 ca adox %edx,%ecx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 82 8f 01 00 00 adcx 0x18f\(%edx\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 42 24 adcx 0x24\(%edx\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx %ecx,%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 94 f4 c0 1d fe ff adcx -0x1e240\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 54 f4 f4 adcx -0xc\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 f6 00 adcx \(%eax\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 82 8f 01 00 00 adox 0x18f\(%edx\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 42 24 adox 0x24\(%edx\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox %ecx,%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 94 f4 c0 1d fe ff adox -0x1e240\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 54 f4 f4 adox -0xc\(%esp,%esi,8\),%edx
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[ ]*[a-f0-9]+: f3 0f 38 f6 00 adox \(%eax\),%eax
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 42 24 adcx 0x24\(%bp,%si\),%eax
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[ ]*[a-f0-9]+: 66 0f 38 f6 d1 adcx %ecx,%edx
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 54 f4 adcx -0xc\(%si\),%edx
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[ ]*[a-f0-9]+: f4 hlt *
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[ ]*[a-f0-9]+: 67 66 0f 38 f6 00 adcx \(%bx,%si\),%eax
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 42 24 adox 0x24\(%bp,%si\),%eax
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[ ]*[a-f0-9]+: f3 0f 38 f6 d1 adox %ecx,%edx
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 54 f4 adox -0xc\(%si\),%edx
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[ ]*[a-f0-9]+: f4 hlt *
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[ ]*[a-f0-9]+: 67 f3 0f 38 f6 00 adox \(%bx,%si\),%eax
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#pass
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@ -17,14 +17,17 @@ _start:
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adoxl (%eax), %eax
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.intel_syntax noprefix
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.rept 2
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adcx eax, DWORD PTR [edx+399]
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adcx eax, DWORD PTR [edx+36]
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adcx edx, ecx
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adcx edx, DWORD PTR [esp+esi*8-123456]
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adcx edx, DWORD PTR [esp+esi*8-12]
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adcx eax, DWORD PTR [eax]
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adox eax, DWORD PTR [edx+399]
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adox eax, DWORD PTR [edx+36]
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adox edx, ecx
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adox edx, DWORD PTR [esp+esi*8-123456]
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adox edx, DWORD PTR [esp+esi*8-12]
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adox eax, DWORD PTR [eax]
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.code16
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.endr
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@ -21,13 +21,29 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 0f ae e9 incsspd ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp QWORD PTR \[ecx\+eax\*1\]
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+[a-f0-9]+: f3 0f 01 6c 01 90 rstorssp QWORD PTR \[ecx\+eax\*1-0x70\]
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+[a-f0-9]+: 0f 38 f6 02 wrssd \[edx\],eax
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+[a-f0-9]+: 0f 38 f6 10 wrssd \[eax\],edx
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
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+[a-f0-9]+: 66 0f 38 f5 3c 2a wrussd \[edx\+ebp\*1\],edi
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+[a-f0-9]+: 66 0f 38 f5 3c 0e wrussd \[esi\+ecx\*1\],edi
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
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+[a-f0-9]+: f3 0f ae 34 44 clrssbsy QWORD PTR \[esp\+eax\*2\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f ae e9 incsspd ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp *
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+[a-f0-9]+: 67 f3 0f 01 6c 01 rstorssp QWORD PTR \[si\+0x1\]
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+[a-f0-9]+: 90 nop *
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+[a-f0-9]+: 67 0f 38 f6 02 wrssd \[bp\+si\],eax
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+[a-f0-9]+: 67 0f 38 f6 10 wrssd \[bx\+si\],edx
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+[a-f0-9]+: 67 66 0f 38 f5 14 wrussd \[si\],edx
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+[a-f0-9]+: 2f das *
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+[a-f0-9]+: 67 66 0f 38 f5 3c wrussd \[si\],edi
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+[a-f0-9]+: 0e push cs
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+[a-f0-9]+: f3 0f 01 e8 setssbsy *
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+[a-f0-9]+: 67 f3 0f ae 34 clrssbsy QWORD PTR \[si\]
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+[a-f0-9]+: 44 inc esp
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+[a-f0-9]+: f3 0f 1e fa endbr64 *
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+[a-f0-9]+: f3 0f 1e fb endbr32 *
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#pass
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@ -19,13 +19,29 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 0f ae e9 incsspd %ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp \(%ecx,%eax,1\)
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+[a-f0-9]+: f3 0f 01 6c 01 90 rstorssp -0x70\(%ecx,%eax,1\)
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+[a-f0-9]+: 0f 38 f6 02 wrssd %eax,\(%edx\)
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+[a-f0-9]+: 0f 38 f6 10 wrssd %edx,\(%eax\)
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
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+[a-f0-9]+: 66 0f 38 f5 3c 2a wrussd %edi,\(%edx,%ebp,1\)
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+[a-f0-9]+: 66 0f 38 f5 3c 0e wrussd %edi,\(%esi,%ecx,1\)
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+[a-f0-9]+: f3 0f 01 e8 setssbsy
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
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+[a-f0-9]+: f3 0f ae 34 44 clrssbsy \(%esp,%eax,2\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f ae e9 incsspd %ecx
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea saveprevssp *
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+[a-f0-9]+: 67 f3 0f 01 6c 01 rstorssp 0x1\(%si\)
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+[a-f0-9]+: 90 nop *
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+[a-f0-9]+: 67 0f 38 f6 02 wrssd %eax,\(%bp,%si\)
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+[a-f0-9]+: 67 0f 38 f6 10 wrssd %edx,\(%bx,%si\)
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+[a-f0-9]+: 67 66 0f 38 f5 14 wrussd %edx,\(%si\)
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+[a-f0-9]+: 2f das *
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+[a-f0-9]+: 67 66 0f 38 f5 3c wrussd %edi,\(%si\)
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+[a-f0-9]+: 0e push %cs
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+[a-f0-9]+: f3 0f 01 e8 setssbsy *
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+[a-f0-9]+: 67 f3 0f ae 34 clrssbsy \(%si\)
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+[a-f0-9]+: 44 inc %esp
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+[a-f0-9]+: f3 0f 1e fa endbr64 *
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+[a-f0-9]+: f3 0f 1e fb endbr32 *
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#pass
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@ -13,15 +13,18 @@ _start:
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endbr32
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.intel_syntax noprefix
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.rept 2
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incsspd ecx
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rdsspd ecx
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saveprevssp
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rstorssp QWORD PTR [ecx + eax]
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rstorssp QWORD PTR [ecx + eax - 0x70]
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wrssd [edx],eax
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wrssd dword ptr [eax],edx
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wrussd [edi + ebp],edx
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wrussd dword ptr [edx + ebp],edi
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wrussd dword ptr [esi + ecx],edi
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setssbsy
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clrssbsy QWORD PTR [esp + eax]
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clrssbsy QWORD PTR [esp + eax * 2]
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endbr64
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endbr32
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.code16
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.endr
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@ -10,6 +10,13 @@ Disassembly of section .text:
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+[a-f0-9]+: f3 66 a7 repz cmpsl %es:\(%di\),%ds:\(%si\)
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+[a-f0-9]+: 66 f3 a5 rep movsl %ds:\(%si\),%es:\(%di\)
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+[a-f0-9]+: 66 f3 a7 repz cmpsl %es:\(%di\),%ds:\(%si\)
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+[a-f0-9]+: 0f 20 d1 mov %cr2,%ecx
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+[a-f0-9]+: 0f 22 d1 mov %ecx,%cr2
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+[a-f0-9]+: 0f 21 d1 mov %d[br]2,%ecx
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+[a-f0-9]+: 0f 23 d1 mov %ecx,%d[br]2
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+[a-f0-9]+: 0f 24 d1 mov %tr2,%ecx
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+[a-f0-9]+: 0f 26 d1 mov %ecx,%tr2
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+[a-f0-9]+: 66 0f c9 bswap %ecx
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+[a-f0-9]+: 66 f3 a5 rep movsl %ds:\(%si\),%es:\(%di\)
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+[a-f0-9]+: 66 f3 a7 repz cmpsl %es:\(%di\),%ds:\(%si\)
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#pass
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@ -4,6 +4,18 @@
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rep; cmpsd
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rep movsd %ds:(%si),%es:(%di)
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rep cmpsd %es:(%di),%ds:(%si)
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mov %cr2, %ecx
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mov %ecx, %cr2
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mov %dr2, %ecx
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mov %ecx, %dr2
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mov %tr2, %ecx
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mov %ecx, %tr2
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bswap %ecx
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.intel_syntax noprefix
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rep movsd dword ptr es:[di], dword ptr ds:[si]
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rep cmpsd dword ptr ds:[si], dword ptr es:[di]
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@ -11,4 +11,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid ebx,OWORD PTR \[ecx\]
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[ ]*[a-f0-9]+: 66 0f 38 80 19 invept ebx,OWORD PTR \[ecx\]
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[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid ebx,OWORD PTR \[ecx\]
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[ ]*[a-f0-9]+: 67 66 0f 38 80 19 invept ebx,OWORD PTR \[bx\+di\]
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[ ]*[a-f0-9]+: 67 66 0f 38 81 19 invvpid ebx,OWORD PTR \[bx\+di\]
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[ ]*[a-f0-9]+: 67 66 0f 38 80 19 invept ebx,OWORD PTR \[bx\+di\]
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[ ]*[a-f0-9]+: 67 66 0f 38 81 19 invvpid ebx,OWORD PTR \[bx\+di\]
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#pass
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@ -10,4 +10,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 66 0f 38 81 19 invvpid \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 66 0f 38 80 19 invept \(%bx,%di\),%ebx
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[ ]*[a-f0-9]+: 67 66 0f 38 81 19 invvpid \(%bx,%di\),%ebx
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[ ]*[a-f0-9]+: 67 66 0f 38 80 19 invept \(%bx,%di\),%ebx
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[ ]*[a-f0-9]+: 67 66 0f 38 81 19 invvpid \(%bx,%di\),%ebx
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#pass
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@ -1,9 +1,15 @@
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# Check EPT instructions
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.text
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_start:
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.rept 2
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invept (%ecx), %ebx
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invvpid (%ecx), %ebx
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.intel_syntax noprefix
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invept ebx, oword ptr [ecx]
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invvpid ebx, oword ptr [ecx]
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.att_syntax prefix
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.code16
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.endr
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@ -16,4 +16,12 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase ebx
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[ ]*[a-f0-9]+: f3 0f ae db wrgsbase ebx
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#pass
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||||
|
|
|
@ -15,4 +15,12 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae c3 rdfsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae cb rdgsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae d3 wrfsbase %ebx
|
||||
[ ]*[a-f0-9]+: f3 0f ae db wrgsbase %ebx
|
||||
#pass
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
.text
|
||||
foo:
|
||||
.rept 2
|
||||
rdfsbase %ebx
|
||||
rdgsbase %ebx
|
||||
wrfsbase %ebx
|
||||
|
@ -12,3 +13,7 @@ foo:
|
|||
rdgsbase ebx
|
||||
wrfsbase ebx
|
||||
wrgsbase ebx
|
||||
|
||||
.att_syntax prefix
|
||||
.code16
|
||||
.endr
|
||||
|
|
|
@ -12,4 +12,7 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid edx,\[bx\+si\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid edx,\[bx\+si\]
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid edx,\[bx\+si\]
|
||||
#pass
|
||||
|
|
|
@ -11,4 +11,7 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
|
||||
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid \(%bx,%si\),%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid \(%bx,%si\),%edx
|
||||
[ ]*[a-f0-9]+: 67 66 0f 38 82 10 invpcid \(%bx,%si\),%edx
|
||||
#pass
|
||||
|
|
|
@ -2,8 +2,14 @@
|
|||
|
||||
.text
|
||||
foo:
|
||||
.rept 2
|
||||
|
||||
invpcid (%eax), %edx
|
||||
|
||||
.intel_syntax noprefix
|
||||
invpcid edx,[eax]
|
||||
invpcid edx,oword ptr [eax]
|
||||
|
||||
.att_syntax prefix
|
||||
.code16
|
||||
.endr
|
||||
|
|
|
@ -16,4 +16,11 @@ Disassembly of section \.text:
|
|||
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri DWORD PTR \[ecx\],eax
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b eax,\[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b ax,\[si\]
|
||||
[ ]*[a-f0-9]+:[ ]*67 0f 38 f9 01[ ]*movdiri DWORD PTR \[bx\+di\],eax
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b ax,\[bx\+di\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 04 67[ ]*movdir64b eax,\[edi\+eiz\*2\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri DWORD PTR \[ecx\],eax
|
||||
[ ]*[a-f0-9]+:[ ]*67 0f 38 f9 01[ ]*movdiri DWORD PTR \[bx\+di\],eax
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b ax,\[bx\+di\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 04 90[ ]*movdir64b eax,\[eax\+edx\*4\]
|
||||
#pass
|
||||
|
|
|
@ -16,4 +16,11 @@ Disassembly of section \.text:
|
|||
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri %eax,\(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 01[ ]*movdir64b \(%ecx\),%eax
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 04[ ]*movdir64b \(%si\),%ax
|
||||
[ ]*[a-f0-9]+:[ ]*67 0f 38 f9 01[ ]*movdiri %eax,\(%bx,%di\)
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b \(%bx,%di\),%ax
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 04 67[ ]*movdir64b \(%edi,%eiz,2\),%eax
|
||||
[ ]*[a-f0-9]+:[ ]*0f 38 f9 01[ ]*movdiri %eax,\(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*67 0f 38 f9 01[ ]*movdiri %eax,\(%bx,%di\)
|
||||
[ ]*[a-f0-9]+:[ ]*67 66 0f 38 f8 01[ ]*movdir64b \(%bx,%di\),%ax
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 f8 04 90[ ]*movdir64b \(%eax,%edx,4\),%eax
|
||||
#pass
|
||||
|
|
|
@ -3,6 +3,7 @@
|
|||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
.rept 2
|
||||
movdiri %eax, (%ecx)
|
||||
movdir64b (%ecx),%eax
|
||||
movdir64b (%si),%ax
|
||||
|
@ -12,3 +13,9 @@ _start:
|
|||
movdiri dword ptr [ecx], eax
|
||||
movdir64b eax,[ecx]
|
||||
movdir64b ax,[si]
|
||||
|
||||
.att_syntax prefix
|
||||
.code16
|
||||
.endr
|
||||
|
||||
nop
|
||||
|
|
|
@ -16,4 +16,11 @@ Disassembly of section \.text:
|
|||
+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
|
||||
+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[ecx\]
|
||||
+[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[ecx\]
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwrite DWORD PTR \[bx\+di\]
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwrite DWORD PTR \[bx\+di\]
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite ecx
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwrite DWORD PTR \[bx\+di\]
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwrite DWORD PTR \[bx\+di\]
|
||||
#pass
|
||||
|
|
|
@ -16,4 +16,11 @@ Disassembly of section \.text:
|
|||
+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
|
||||
+[a-f0-9]+: f3 0f ae 21 ptwritel \(%ecx\)
|
||||
+[a-f0-9]+: f3 0f ae 21 ptwritel \(%ecx\)
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwritel \(%bx,%di\)
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwritel \(%bx,%di\)
|
||||
+[a-f0-9]+: f3 0f ae e1 ptwrite %ecx
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwritel \(%bx,%di\)
|
||||
+[a-f0-9]+: 67 f3 0f ae 21 ptwritel \(%bx,%di\)
|
||||
#pass
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
.text
|
||||
_start:
|
||||
.rept 2
|
||||
ptwrite %ecx
|
||||
ptwritel %ecx
|
||||
ptwrite (%ecx)
|
||||
|
@ -11,3 +12,7 @@ _start:
|
|||
ptwrite ecx
|
||||
ptwrite [ecx]
|
||||
ptwrite DWORD PTR [ecx]
|
||||
|
||||
.att_syntax prefix
|
||||
.code16
|
||||
.endr
|
||||
|
|
|
@ -8,4 +8,5 @@ Disassembly of section .text:
|
|||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f8[ ]*rdpid eax
|
||||
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f9[ ]*rdpid ecx
|
||||
#pass
|
||||
|
|
|
@ -8,4 +8,5 @@ Disassembly of section .text:
|
|||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f8[ ]*rdpid %eax
|
||||
[ ]*[a-f0-9]+:[ ]*f3 0f c7 f9[ ]*rdpid %ecx
|
||||
#pass
|
||||
|
|
|
@ -3,3 +3,6 @@
|
|||
.text
|
||||
_start:
|
||||
rdpid %eax
|
||||
|
||||
.code16
|
||||
rdpid %ecx
|
||||
|
|
|
@ -164,4 +164,23 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f fb c1 psubq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 67 66 0f fb 00 psubq \(%eax\),%xmm0
|
||||
[ ]*[a-f0-9]+: 0f 58 2f addps \(%bx\),%xmm5
|
||||
[ ]*[a-f0-9]+: f3 0f 2a d9 cvtsi2ss %ecx,%xmm3
|
||||
[ ]*[a-f0-9]+: f3 0f 2d cb cvtss2si %xmm3,%ecx
|
||||
[ ]*[a-f0-9]+: f3 0f 2c cb cvttss2si %xmm3,%ecx
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 17 ca 00 extractps \$0x0,%xmm1,%edx
|
||||
[ ]*[a-f0-9]+: 0f 50 ca movmskps %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 14 ca 00 pextrb \$0x0,%xmm1,%edx
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 16 ca 00 pextrd \$0x0,%xmm1,%edx
|
||||
[ ]*[a-f0-9]+: 0f c5 d1 00 pextrw \$0x0,%mm1,%edx
|
||||
[ ]*[a-f0-9]+: 66 0f c5 d1 00 pextrw \$0x0,%xmm1,%edx
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 20 d1 00 pinsrb \$0x0,%ecx,%xmm2
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 22 d1 00 pinsrd \$0x0,%ecx,%xmm2
|
||||
[ ]*[a-f0-9]+: 0f c4 d1 00 pinsrw \$0x0,%ecx,%mm2
|
||||
[ ]*[a-f0-9]+: 66 0f c4 d1 00 pinsrw \$0x0,%ecx,%xmm2
|
||||
[ ]*[a-f0-9]+: 66 0f d7 d3 pmovmskb %xmm3,%edx
|
||||
[ ]*[a-f0-9]+: f3 0f 2a 05 cvtsi2ssl? \(%di\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 17 0d 00 extractps \$0x0,%xmm1,\(%di\)
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 21 05 00 insertps \$0x0,\(%di\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 16 0d 00 pextrd \$0x0,%xmm1,\(%di\)
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 22 05 00 pinsrd \$0x0,\(%di\),%xmm0
|
||||
#pass
|
||||
|
|
|
@ -4,4 +4,26 @@
|
|||
.include "sse2.s"
|
||||
.att_syntax prefix
|
||||
|
||||
# also a few SSE* insns
|
||||
addps (%bx),%xmm5
|
||||
cvtsi2ss %ecx,%xmm3
|
||||
cvtss2si %xmm3,%ecx
|
||||
cvttss2si %xmm3,%ecx
|
||||
extractps $0,%xmm1,%edx
|
||||
movmskps %xmm2,%ecx
|
||||
pextrb $0,%xmm1,%edx
|
||||
pextrd $0,%xmm1,%edx
|
||||
pextrw $0,%mm1,%edx
|
||||
pextrw $0,%xmm1,%edx
|
||||
pinsrb $0,%ecx,%xmm2
|
||||
pinsrd $0,%ecx,%xmm2
|
||||
pinsrw $0,%ecx,%mm2
|
||||
pinsrw $0,%ecx,%xmm2
|
||||
pmovmskb %xmm3,%edx
|
||||
|
||||
.intel_syntax noprefix
|
||||
cvtsi2ss xmm0, dword ptr [di]
|
||||
extractps dword ptr [di], xmm1, 0
|
||||
insertps xmm0, dword ptr [di], 0
|
||||
pextrd dword ptr [di], xmm1, 0
|
||||
pinsrd xmm0, dword ptr [di], 0
|
||||
|
|
|
@ -22,4 +22,20 @@ Disassembly of section .text:
|
|||
29: 0f 79 d8 [ ]*vmwrite %eax,%ebx
|
||||
2c: 0f 79 18 [ ]*vmwrite \(%eax\),%ebx
|
||||
2f: 0f 79 18 [ ]*vmwrite \(%eax\),%ebx
|
||||
...
|
||||
[ ]*[a-f0-9]+: 0f 01 c1[ ]*vmcall *
|
||||
[ ]*[a-f0-9]+: 0f 01 c2[ ]*vmlaunch *
|
||||
[ ]*[a-f0-9]+: 0f 01 c3[ ]*vmresume *
|
||||
[ ]*[a-f0-9]+: 0f 01 c4[ ]*vmxoff *
|
||||
[ ]*[a-f0-9]+: 67 66 0f c7 30[ ]*vmclear \(%bx,%si\)
|
||||
[ ]*[a-f0-9]+: 67 0f c7 30[ ]*vmptrld \(%bx,%si\)
|
||||
[ ]*[a-f0-9]+: 67 0f c7 38[ ]*vmptrst \(%bx,%si\)
|
||||
[ ]*[a-f0-9]+: 67 f3 0f c7 30[ ]*vmxon \(%bx,%si\)
|
||||
[ ]*[a-f0-9]+: 0f 78 c3[ ]*vmread %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f 78 c3[ ]*vmread %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 67 0f 78 03[ ]*vmread %eax,\(%bp,%di\)
|
||||
[ ]*[a-f0-9]+: 67 0f 78 03[ ]*vmread %eax,\(%bp,%di\)
|
||||
[ ]*[a-f0-9]+: 0f 79 d8[ ]*vmwrite %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 0f 79 d8[ ]*vmwrite %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 67 0f 79 18[ ]*vmwrite \(%bx,%si\),%ebx
|
||||
[ ]*[a-f0-9]+: 67 0f 79 18[ ]*vmwrite \(%bx,%si\),%ebx
|
||||
#pass
|
||||
|
|
|
@ -2,6 +2,8 @@
|
|||
|
||||
.text
|
||||
foo:
|
||||
.rept 2
|
||||
|
||||
vmcall
|
||||
vmlaunch
|
||||
vmresume
|
||||
|
@ -18,4 +20,7 @@ foo:
|
|||
vmwritel %eax,%ebx
|
||||
vmwrite (%eax),%ebx
|
||||
vmwritel (%eax),%ebx
|
||||
|
||||
.code16
|
||||
.endr
|
||||
.p2align 4,0
|
||||
|
|
|
@ -1,3 +1,11 @@
|
|||
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
|
||||
invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
|
||||
adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
|
||||
(ptwrite): Split into non-64-bit and 64-bit forms.
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2020-03-06 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
|
||||
|
|
|
@ -1294,7 +1294,7 @@ movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreS
|
|||
movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
|
||||
movlps, 2, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
|
||||
movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
|
||||
movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
|
||||
movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
|
||||
movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
|
||||
movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
|
||||
movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex }
|
||||
|
@ -1588,7 +1588,7 @@ movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
|
|||
mwait, 0, 0xf01c9, None, 3, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { 0 }
|
||||
// mwait is very special. AX and CX are always 32 bits.
|
||||
// The 64-bit form exists only for compatibility with older gas.
|
||||
mwait, 2, 0xf01c9, None, 3, CpuSSE3, CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Acc|Dword|Qword, RegC|Dword|Qword }
|
||||
mwait, 2, 0xf01c9, None, 3, CpuSSE3, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Acc|Dword|Qword, RegC|Dword|Qword }
|
||||
|
||||
// VMX instructions.
|
||||
|
||||
|
@ -1598,9 +1598,9 @@ vmlaunch, 0, 0xf01c2, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N
|
|||
vmresume, 0, 0xf01c3, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
vmptrld, 1, 0xfc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
|
||||
vmptrst, 1, 0xfc7, 0x7, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
|
||||
vmread, 2, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vmread, 2, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Unspecified|BaseIndex }
|
||||
vmread, 2, 0xf78, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex }
|
||||
vmwrite, 2, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, Reg32 }
|
||||
vmwrite, 2, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32 }
|
||||
vmwrite, 2, 0xf79, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 }
|
||||
vmxoff, 0, 0xf01c4, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
|
||||
|
@ -1615,14 +1615,14 @@ getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
|
|||
|
||||
// EPT instructions.
|
||||
|
||||
invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invept, 2, 0x660f3880, None, 3, CpuEPT|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
|
||||
invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
|
||||
|
||||
// INVPCID instruction
|
||||
|
||||
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
|
||||
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
|
||||
|
||||
// SSSE3 instructions.
|
||||
|
@ -2485,11 +2485,11 @@ vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|
|
|||
|
||||
// FSGSBASE, RDRND and F16C
|
||||
|
||||
rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
|
||||
wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
|
||||
vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
|
||||
|
@ -2880,8 +2880,8 @@ xcryptofb, 0, 0xf30fa7e8, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
|
|||
xstore, 0, 0xfa7c0, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
|
||||
|
||||
// Multy-precision Add Carry, rdseed instructions.
|
||||
adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
|
||||
|
||||
// SMAP instructions.
|
||||
|
@ -4702,7 +4702,7 @@ monitorx, 3, 0xf01fa, None, 3, CpuMWAITX|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qwo
|
|||
|
||||
mwaitx, 0, 0xf01fb, None, 3, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
// The 64-bit form exists only for compatibility with older gas.
|
||||
mwaitx, 3, 0xf01fb, None, 3, CpuMWAITX, CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
|
||||
mwaitx, 3, 0xf01fb, None, 3, CpuMWAITX, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
|
||||
|
||||
// MONITORX/MWAITX instructions end
|
||||
|
||||
|
@ -4715,14 +4715,15 @@ wrpkru, 0, 0xf01ef, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N
|
|||
|
||||
// RDPID instructions.
|
||||
|
||||
rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
|
||||
rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
|
||||
rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
|
||||
|
||||
// RDPID instructions end.
|
||||
|
||||
// PTWRITE instructions.
|
||||
|
||||
ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex }
|
||||
ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex }
|
||||
ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
// PTWRITE instructions end.
|
||||
|
||||
|
@ -4778,8 +4779,7 @@ cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|No_bSuf|No_wS
|
|||
|
||||
// MOVDIR[I,64B] instructions.
|
||||
|
||||
movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
|
||||
|
||||
movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
|
||||
movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
||||
// MOVEDIR instructions end.
|
||||
|
|
|
@ -12695,7 +12695,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
@ -16645,7 +16645,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -16731,7 +16731,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
|
@ -16759,7 +16759,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0,
|
||||
|
@ -16835,7 +16835,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
@ -16863,7 +16863,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
@ -16891,7 +16891,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
@ -39717,7 +39717,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -39729,7 +39729,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -39753,7 +39753,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -39765,7 +39765,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -47333,7 +47333,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
|
||||
|
@ -47347,7 +47347,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
|
||||
|
@ -58051,7 +58051,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
@ -58091,7 +58091,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
|
@ -58114,11 +58114,23 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ "ptwrite", 0xf30fae, 0x4, 2, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ "incsspd", 0xf30fae, 0x5, 2, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
@ -58419,7 +58431,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
|
||||
|
|
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Reference in New Issue