* config/tc-ppc.c (parse_cpu): Handle "-mpower5".
(md_show_usage): Document it. (ppc_setup_opcodes): Insert POWER5 mnemonics. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower5".
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@ -1,3 +1,10 @@
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2005-05-19 Anton Blanchard <anton@samba.org>
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* config/tc-ppc.c (parse_cpu): Handle "-mpower5".
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(md_show_usage): Document it.
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(ppc_setup_opcodes): Insert POWER5 mnemonics.
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* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower5".
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2005-05-19 Jan Beulich <jbeulich@novell.com>
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2005-05-19 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c (dot_endp): Don't use global symbol for unwind
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* config/tc-ia64.c (dot_endp): Don't use global symbol for unwind
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@ -906,6 +906,12 @@ parse_cpu (const char *arg)
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4);
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4);
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}
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}
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else if (strcmp (arg, "power5") == 0)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5);
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}
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/* -mcom means assemble for the common intersection between Power
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/* -mcom means assemble for the common intersection between Power
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and PowerPC. At present, we just allow the union, rather
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and PowerPC. At present, we just allow the union, rather
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than the intersection. */
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than the intersection. */
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@ -1100,6 +1106,7 @@ PowerPC options:\n\
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-mbooke64 generate code for 64-bit PowerPC BookE\n\
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-mbooke64 generate code for 64-bit PowerPC BookE\n\
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-mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\
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-mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\
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-mpower4 generate code for Power4 architecture\n\
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-mpower4 generate code for Power4 architecture\n\
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-mpower5 generate code for Power5 architecture\n\
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-mcom generate code Power/PowerPC common instructions\n\
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-mcom generate code Power/PowerPC common instructions\n\
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-many generate code for any architecture (PWR/PWRX/PPC)\n"));
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-many generate code for any architecture (PWR/PWRX/PPC)\n"));
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fprintf (stream, _("\
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fprintf (stream, _("\
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@ -1255,7 +1262,10 @@ ppc_setup_opcodes (void)
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|| (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
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|| (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
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&& ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
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&& ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
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|| ((op->flags & PPC_OPCODE_POWER4)
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|| ((op->flags & PPC_OPCODE_POWER4)
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== (ppc_cpu & PPC_OPCODE_POWER4))))
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== (ppc_cpu & PPC_OPCODE_POWER4)))
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&& ((op->flags & PPC_OPCODE_POWER5) == 0
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|| ((op->flags & PPC_OPCODE_POWER5)
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== (ppc_cpu & PPC_OPCODE_POWER5))))
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{
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{
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const char *retval;
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const char *retval;
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@ -73,6 +73,9 @@ Generate code for processors with AltiVec instructions.
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@item -mpower4
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@item -mpower4
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Generate code for Power4 architecture.
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Generate code for Power4 architecture.
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@item -mpower5
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Generate code for Power5 architecture.
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@item -mcom
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@item -mcom
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Generate code Power/PowerPC common instructions.
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Generate code Power/PowerPC common instructions.
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