[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions
This patch makes changes to the <spec_reg> operand for VMRS and VMSR instructions as per the Armv8.1-M Mainline. New <spec_reg> options to support are: 0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags. 0b1100: VPR, privileged only access to the VPR register. 0b1101: P0, access to VPR.P0 predicate fields 0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating point context. 0b1111: FPCXT_S, enables saving and restoring of Secure floating point context *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (parse_operands): Update case OP_RVC to parse p0 and P0. (do_vmrs): Add checks for valid operands with respect to cpu and fpu options. (do_vmsr): Likewise. (reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS and FPCXT_S. * testsuite/gas/arm/armv8_1-m-spec-reg.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg.s: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New. * testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values. * testsuite/gas/arm/vfp1xD_t2.d: Likewise. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (coprocessor_opcodes): New instructions for VMRS and VMSR with the new operands.
This commit is contained in:
Sudakshina Das
parent
e39c1607a2
commit
ba6cd17f0a
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@ -1,3 +1,23 @@
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (parse_operands): Update case OP_RVC to
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parse p0 and P0.
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(do_vmrs): Add checks for valid operands with respect to
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cpu and fpu options.
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(do_vmsr): Likewise.
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(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
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and FPCXT_S.
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* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
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* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
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* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
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* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (TOGGLE_BIT): New.
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@ -7236,7 +7236,20 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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break;
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/* Also accept generic coprocessor regs for unknown registers. */
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coproc_reg:
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po_reg_or_fail (REG_TYPE_CN);
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po_reg_or_goto (REG_TYPE_CN, vpr_po);
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break;
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/* Also accept P0 or p0 for VPR.P0. Since P0 is already an
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existing register with a value of 0, this seems like the
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best way to parse P0. */
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vpr_po:
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if (strncasecmp (str, "P0", 2) == 0)
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{
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str += 2;
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inst.operands[i].isreg = 1;
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inst.operands[i].reg = 13;
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}
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else
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goto failure;
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break;
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case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
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case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
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@ -9836,10 +9849,42 @@ do_vmrs (void)
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return;
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}
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/* MVFR2 is only valid at ARMv8-A. */
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if (inst.operands[1].reg == 5)
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
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_(BAD_FPU));
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switch (inst.operands[1].reg)
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{
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/* MVFR2 is only valid for Armv8-A. */
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case 5:
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
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_(BAD_FPU));
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break;
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/* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
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case 1: /* fpscr. */
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constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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|| ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
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_(BAD_FPU));
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break;
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case 14: /* fpcxt_ns. */
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case 15: /* fpcxt_s. */
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
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_("selected processor does not support instruction"));
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break;
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case 2: /* fpscr_nzcvqc. */
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case 12: /* vpr. */
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case 13: /* p0. */
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
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|| (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
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_("selected processor does not support instruction"));
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if (inst.operands[0].reg != 2
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
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break;
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default:
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break;
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}
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/* APSR_ sets isvec. All other refs to PC are illegal. */
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if (!inst.operands[0].isvec && Rt == REG_PC)
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@ -9867,10 +9912,42 @@ do_vmsr (void)
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return;
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}
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/* MVFR2 is only valid for ARMv8-A. */
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if (inst.operands[0].reg == 5)
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
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_(BAD_FPU));
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switch (inst.operands[0].reg)
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{
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/* MVFR2 is only valid for Armv8-A. */
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case 5:
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
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_(BAD_FPU));
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break;
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/* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
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case 1: /* fpcr. */
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constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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|| ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
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_(BAD_FPU));
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break;
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case 14: /* fpcxt_ns. */
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case 15: /* fpcxt_s. */
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
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_("selected processor does not support instruction"));
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break;
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case 2: /* fpscr_nzcvqc. */
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case 12: /* vpr. */
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case 13: /* p0. */
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
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|| (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
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_("selected processor does not support instruction"));
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if (inst.operands[0].reg != 2
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&& !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
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break;
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default:
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break;
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}
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/* If we get through parsing the register name, we just insert the number
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generated into the instruction without further validation. */
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@ -22813,6 +22890,10 @@ static const struct reg_entry reg_names[] =
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REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
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REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
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REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
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REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
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REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
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REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
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REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
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/* Maverick DSP coprocessor registers. */
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REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
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@ -24440,11 +24521,14 @@ static const struct asm_opcode insns[] =
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v6t2
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mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs),
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mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr),
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#undef THUMB_VARIANT
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/* Moves and type conversions. */
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cCE("fmstat", ef1fa10, 0, (), noargs),
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cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
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cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
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cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
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cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
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cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
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@ -0,0 +1,4 @@
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#name: Invalid VMSR/VMRS no mve or fp
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#source: armv8_1-m-spec-reg.s
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#as: -march=armv8.1-m.main
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#error_output: armv8_1-m-spec-reg-bad1.l
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@ -0,0 +1,9 @@
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.*: Assembler messages:
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.*: selected FPU does not support instruction -- `vmrs r0,FPSCR'
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.*: selected processor does not support instruction -- `vmrs r1,FPSCR_nzcvqc'
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.*: selected processor does not support instruction -- `vmrs r2,VPR'
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.*: selected processor does not support instruction -- `vmrs r3,P0'
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.*: selected FPU does not support instruction -- `vmsr fpscr,r0'
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.*: selected processor does not support instruction -- `vmsr fpscr_nzcvqc,r1'
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.*: selected processor does not support instruction -- `vmsr vpr,r2'
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.*: selected processor does not support instruction -- `vmsr p0,r3'
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@ -0,0 +1,4 @@
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#name: Invalid VMSR/VMRS no mve
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#source: armv8_1-m-spec-reg.s
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#as: -march=armv8.1-m.main+fp
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#warning_output: armv8_1-m-spec-reg-bad2.l
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@ -0,0 +1,5 @@
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.*: Assembler messages:
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.*: Warning: accessing MVE system register without MVE is UNPREDICTABLE
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.*: Warning: accessing MVE system register without MVE is UNPREDICTABLE
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.*: Warning: accessing MVE system register without MVE is UNPREDICTABLE
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.*: Warning: accessing MVE system register without MVE is UNPREDICTABLE
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@ -0,0 +1,4 @@
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#name: Invalid VMSR/VMRS Only FPSCR allowed
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#source: armv8_1-m-spec-reg.s
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#as: -march=armv6t2 -mfpu=vfpxd
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#error_output: armv8_1-m-spec-reg-bad3.l
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@ -0,0 +1,11 @@
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.*: Assembler messages:
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.*: selected processor does not support instruction -- `vmrs r1,FPSCR_nzcvqc'
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.*: selected processor does not support instruction -- `vmrs r2,VPR'
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.*: selected processor does not support instruction -- `vmrs r3,P0'
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.*: selected processor does not support instruction -- `vmrs r4,FPCXT_NS'
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.*: selected processor does not support instruction -- `vmrs r5,FPCXT_S'
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.*: selected processor does not support instruction -- `vmsr fpscr_nzcvqc,r1'
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.*: selected processor does not support instruction -- `vmsr vpr,r2'
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.*: selected processor does not support instruction -- `vmsr p0,r3'
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.*: selected processor does not support instruction -- `vmsr fpcxt_ns,r4'
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.*: selected processor does not support instruction -- `vmsr fpcxt_s,r5'
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@ -0,0 +1,20 @@
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#name: Valid Armv8.1-M Mainline <spec_reg> change
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#source: armv8_1-m-spec-reg.s
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#as: -march=armv8.1-m.main+mve
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#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> eef1 0a10 vmrs r0, fpscr
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0[0-9a-f]+ <[^>]+> eef2 1a10 vmrs r1, fpscr_nzcvqc
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0[0-9a-f]+ <[^>]+> eefc 2a10 vmrs r2, vpr
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0[0-9a-f]+ <[^>]+> eefd 3a10 vmrs r3, p0
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0[0-9a-f]+ <[^>]+> eefe 4a10 vmrs r4, fpcxt_ns
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0[0-9a-f]+ <[^>]+> eeff 5a10 vmrs r5, fpcxt_s
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0[0-9a-f]+ <[^>]+> eee1 0a10 vmsr fpscr, r0
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0[0-9a-f]+ <[^>]+> eee2 1a10 vmsr fpscr_nzcvqc, r1
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0[0-9a-f]+ <[^>]+> eeec 2a10 vmsr vpr, r2
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0[0-9a-f]+ <[^>]+> eeed 3a10 vmsr p0, r3
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0[0-9a-f]+ <[^>]+> eeee 4a10 vmsr fpcxt_ns, r4
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0[0-9a-f]+ <[^>]+> eeef 5a10 vmsr fpcxt_s, r5
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@ -0,0 +1,15 @@
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.syntax unified
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func:
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vmrs r0, FPSCR
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vmrs r1, FPSCR_nzcvqc
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vmrs r2, VPR
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vmrs r3, P0
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vmrs r4, FPCXT_NS
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vmrs r5, FPCXT_S
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vmsr fpscr, r0
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vmsr fpscr_nzcvqc, r1
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vmsr vpr, r2
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vmsr p0, r3
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vmsr fpcxt_ns, r4
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vmsr fpcxt_s, r5
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@ -243,12 +243,12 @@ Disassembly of section .text:
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0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
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0+3a8 <[^>]*> eef70a10 (vmrs|fmrx) r0, mvfr0
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0+3ac <[^>]*> eef60a10 (vmrs|fmrx) r0, mvfr1
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0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, <impl def 0xc>
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0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, (vpr|<impl def 0xc>)
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0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 @ Impl def
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0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
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0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0
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0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0
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0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) <impl def 0xc>, r0
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0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) (vpr|<impl def 0xc>), r0
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0+3c8 <[^>]*> eef10a10 vmrs r0, fpscr
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0+3cc <[^>]*> eef11a10 vmrs r1, fpscr
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0+3d0 <[^>]*> eef12a10 vmrs r2, fpscr
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@ -282,14 +282,14 @@ Disassembly of section .text:
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0+440 <[^>]*> eee82a10 vmsr fpexc, r2
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0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def
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0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def
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0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>), r5
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0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>|fpcxt_s), r5
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0+450 <[^>]*> eef03a10 vmrs r3, fpsid
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0+454 <[^>]*> eef64a10 vmrs r4, mvfr1
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0+458 <[^>]*> eef75a10 vmrs r5, mvfr0
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0+45c <[^>]*> eef86a10 vmrs r6, fpexc
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0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def
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0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def
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0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>)
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0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>|fpcxt_s)
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0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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@ -257,12 +257,12 @@ Disassembly of section .text:
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0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def
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0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0
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0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1
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0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, <impl def 0xc>
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0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (<impl def 0xc>|vpr)
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0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def
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0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def
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0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0
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0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0
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0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) <impl def 0xc>, r0
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0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (<impl def 0xc>|vpr), r0
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0+3e4 <[^>]*> bf00 nop
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0+3e6 <[^>]*> bf00 nop
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0+3e8 <[^>]*> bf00 nop
|
||||
|
|
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|||
|
|
@ -1,3 +1,8 @@
|
|||
2019-05-21 Sudakshina Das <sudi.das@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
|
||||
and VMSR with the new operands.
|
||||
|
||||
2019-05-21 Sudakshina Das <sudi.das@arm.com>
|
||||
|
||||
* arm-dis.c (enum mve_instructions): New enum
|
||||
|
|
|
|||
|
|
@ -809,8 +809,10 @@ static const struct sopcode32 coprocessor_opcodes[] =
|
|||
/* Floating point coprocessor (VFP) instructions. */
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
|
||||
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
|
|
@ -823,12 +825,22 @@ static const struct sopcode32 coprocessor_opcodes[] =
|
|||
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_MVE),
|
||||
0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_MVE),
|
||||
0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
|
||||
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
|
||||
0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
|
|
@ -841,6 +853,14 @@ static const struct sopcode32 coprocessor_opcodes[] =
|
|||
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
|
||||
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_MVE),
|
||||
0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_MVE),
|
||||
0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
|
||||
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||
0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
||||
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
|
||||
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
|
||||
|
|
|
|||
Loading…
Reference in New Issue