* avr-dis.c: completely rewritten.
This commit is contained in:
Denis Chertykov
parent
1188e08253
commit
bab84c47ec
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@ -1,3 +1,7 @@
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Wed Jun 7 21:36:45 2000 Denis Chertykov <denisc@overta.ru>
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* avr-dis.c: completely rewritten.
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2000-06-02 Kazu Hirata <kazu@hxi.com>=0A=
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* h8300-dis.c: Follow the GNU coding style.
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@ -17,223 +17,200 @@ You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <assert.h>
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opintl.h"
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned long u32;
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#define IFMASK(a,b) ((opcode & (a)) == (b))
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static char* SREG_flags = "CZNVSHTI";
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static char* sect94[] = {"COM","NEG","SWAP","INC",0,"ASR","LSR","ROR",
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0,0,"DEC",0,0,0,0,0};
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static char* sect98[] = {"CBI","SBIC","SBI","SBIS"};
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static char* branchs[] = {
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"BRCS","BREQ","BRMI","BRVS",
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"BRLT","BRHS","BRTS","BRIE",
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"BRCC","BRNE","BRPL","BRVC",
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"BRGE","BRHC","BRTC","BRID"
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struct avr_opcodes_s
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{
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char *name;
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char *constraints;
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char *opcode;
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int insn_size; /* in words */
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int isa;
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unsigned int bin_opcode;
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unsigned int bin_mask;
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};
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static char* last4[] = {"BLD","BST","SBRC","SBRS"};
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#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
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{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},
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struct avr_opcodes_s avr_opcodes[] =
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{
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#include "opcode/avr.h"
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{NULL, NULL, NULL, 0, 0, 0, 0}
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};
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static void dispLDD PARAMS ((u16, char *));
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static void avr_operand (unsigned int insn, unsigned int insn2,
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unsigned int pc, int constraint, char *buf,
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char *comment, int regs);
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static void
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dispLDD (opcode, dest)
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u16 opcode;
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char *dest;
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avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
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unsigned int insn;
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unsigned int insn2;
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unsigned int pc;
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int constraint;
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char *buf;
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char *comment;
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int regs;
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{
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opcode = (((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7)
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| (opcode & 7));
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sprintf(dest, "%d", opcode);
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switch (constraint)
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{
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/* Any register operand. */
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case 'r':
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if (regs)
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insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
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else
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insn = (insn & 0x01f0) >> 4; /* destination register */
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sprintf (buf, "r%d", insn);
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break;
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case 'd':
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if (regs)
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sprintf (buf, "r%d", 16 + (insn & 0xf));
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else
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sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
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break;
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case 'w':
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sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
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break;
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case 'a':
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if (regs)
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sprintf (buf, "r%d", 16 + (insn & 7));
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else
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sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
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break;
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case 'v':
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if (regs)
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sprintf (buf, "r%d", (insn & 0xf) * 2);
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else
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sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
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break;
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case 'e':
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if (insn & 0x2)
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*buf++ = '-';
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switch ((insn >> 2) & 0x3)
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{
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case 0: *buf++ = 'Z'; break;
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case 2: *buf++ = 'Y'; break;
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case 3: *buf++ = 'X'; break;
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default: buf += sprintf (buf, _ (" unknown register ")); break;
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}
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if (insn & 0x1)
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*buf++ = '+';
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*buf = '\0';
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break;
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case 'z':
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*buf++ = 'Z';
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if (insn & 0x1)
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*buf++ = '+';
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*buf = '\0';
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break;
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case 'b':
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{
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unsigned int x = insn;
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x = (insn & 7);
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x |= (insn >> 7) & (3 << 3);
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x |= (insn >> 8) & (1 << 5);
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if (insn & 0x8)
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*buf++ = 'Y';
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else
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*buf++ = 'Z';
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sprintf (buf, "+%d", x);
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sprintf (comment, "0x%02x", x);
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}
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break;
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case 'h':
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sprintf (buf, "0x%x%x", (insn & 1) | ((insn & (0x1f << 4)) >> 3), insn2);
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break;
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case 'L':
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{
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int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
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sprintf (buf, ".%+-8d", rel_addr);
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sprintf (comment, "0x%x", pc + 2 + rel_addr);
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}
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break;
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case 'l':
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{
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int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
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sprintf (buf, ".%+-8d", rel_addr);
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sprintf (comment, "0x%x", pc + 2 + rel_addr);
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}
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break;
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case 'i':
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sprintf (buf, "0x%04X", insn2);
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break;
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case 'M':
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sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
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sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
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break;
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case 'n':
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sprintf (buf, _ ("Internal disassembler error"));
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break;
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case 'K':
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sprintf (buf, "%d", (insn & 0xf) | ((insn >> 2) & 0x30));
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break;
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case 's':
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sprintf (buf, "%d", insn & 7);
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break;
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case 'S':
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sprintf (buf, "%d", (insn >> 4) & 7);
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break;
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case 'P':
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{
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unsigned int x;
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x = (insn & 0xf);
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x |= (insn >> 5) & 0x30;
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sprintf (buf, "0x%02x", x);
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sprintf (comment, "%d", x);
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}
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break;
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case 'p':
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{
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unsigned int x;
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x = (insn >> 3) & 0x1f;
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sprintf (buf, "0x%02x", x);
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sprintf (comment, "%d", x);
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}
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break;
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case '?':
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*buf = '\0';
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break;
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default:
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sprintf (buf, _ ("unknown constraint `%c'"), constraint);
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}
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}
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static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
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static void regPP PARAMS ((u16, char *));
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static void
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regPP (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = ((opcode & 0x0600) >> 5) | (opcode & 0xf);
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sprintf(dest, "0x%02X", opcode);
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}
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static void reg50 PARAMS ((u16, char *));
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static void
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reg50 (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = (opcode & 0x01f0) >> 4;
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sprintf(dest, "R%d", opcode);
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}
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static void reg104 PARAMS ((u16, char *));
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static void
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reg104 (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = (opcode & 0xf) | ((opcode & 0x0200) >> 5);
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sprintf(dest, "R%d", opcode);
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}
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static void reg40 PARAMS ((u16, char *));
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static void
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reg40 (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = (opcode & 0xf0) >> 4;
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sprintf(dest, "R%d", opcode + 16);
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}
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static void reg20w PARAMS ((u16, char *));
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static void
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reg20w (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = (opcode & 0x30) >> 4;
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sprintf(dest, "R%d", 24 + opcode * 2);
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}
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static void reg_fmul_d PARAMS ((u16, char *));
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static void
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reg_fmul_d (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 16 + ((opcode >> 4) & 7));
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}
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static void reg_fmul_r PARAMS ((u16, char *));
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static void
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reg_fmul_r (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 16 + (opcode & 7));
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}
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static void reg_muls_d PARAMS ((u16, char *));
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static void
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reg_muls_d (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 16 + ((opcode >> 4) & 0xf));
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}
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static void reg_muls_r PARAMS ((u16, char *));
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static void
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reg_muls_r (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 16 + (opcode & 0xf));
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}
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static void reg_movw_d PARAMS ((u16, char *));
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static void
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reg_movw_d (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 2 * ((opcode >> 4) & 0xf));
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}
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static void reg_movw_r PARAMS ((u16, char *));
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static void
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reg_movw_r (opcode, dest)
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u16 opcode;
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char *dest;
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{
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sprintf(dest, "R%d", 2 * (opcode & 0xf));
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}
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static void lit404 PARAMS ((u16, char *));
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static void
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lit404 (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
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sprintf(dest, "0x%02X", opcode);
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}
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static void lit204 PARAMS ((u16, char *));
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static void
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lit204 (opcode, dest)
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u16 opcode;
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char *dest;
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{
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opcode = ((opcode & 0xc0) >> 2) | (opcode & 0xf);
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sprintf(dest, "0x%02X", opcode);
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}
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static void add0fff PARAMS ((u16, char *, int));
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static void
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add0fff (op, dest, pc)
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u16 op;
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char *dest;
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int pc;
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{
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int rel_addr = (((op & 0xfff) ^ 0x800) - 0x800) * 2;
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sprintf(dest, ".%+-8d ; 0x%06X", rel_addr, pc + 2 + rel_addr);
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}
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static void add03f8 PARAMS ((u16, char *, int));
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static void
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add03f8 (op, dest, pc)
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u16 op;
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char *dest;
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int pc;
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{
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int rel_addr = ((((op >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
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sprintf(dest, ".%+-8d ; 0x%06X", rel_addr, pc + 2 + rel_addr);
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}
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static u16 avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
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static u16
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static unsigned short
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avrdis_opcode (addr, info)
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bfd_vma addr;
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disassemble_info *info;
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@ -255,402 +232,87 @@ print_insn_avr(addr, info)
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bfd_vma addr;
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disassemble_info *info;
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{
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char rr[200];
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char rd[200];
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u16 opcode;
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unsigned int insn, insn2;
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struct avr_opcodes_s *opcode;
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void *stream = info->stream;
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fprintf_ftype prin = info->fprintf_func;
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static int initialized;
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int cmd_len = 2;
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opcode = avrdis_opcode (addr, info);
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if (IFMASK(0xd000, 0x8000))
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if (!initialized)
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{
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char letter;
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reg50(opcode, rd);
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dispLDD(opcode, rr);
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if (opcode & 8)
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letter = 'Y';
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else
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letter = 'Z';
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if (opcode & 0x0200)
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(*prin) (stream, " STD %c+%s,%s", letter, rr, rd);
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else
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(*prin) (stream, " LDD %s,%c+%s", rd, letter, rr);
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initialized = 1;
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for (opcode = avr_opcodes; opcode->name; opcode++)
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{
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char * s;
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unsigned int bin = 0;
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unsigned int mask = 0;
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for (s = opcode->opcode; *s; ++s)
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{
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bin <<= 1;
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mask <<= 1;
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bin |= (*s == '1');
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mask |= (*s == '1' || *s == '0');
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}
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assert (s - opcode->opcode == 16);
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assert (opcode->bin_opcode == bin);
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opcode->bin_mask = mask;
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}
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}
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insn = avrdis_opcode (addr, info);
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for (opcode = avr_opcodes; opcode->name; opcode++)
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{
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if ((insn & opcode->bin_mask) == opcode->bin_opcode)
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break;
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}
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if (opcode->name)
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{
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char op1[20], op2[20], comment1[40], comment2[40];
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char *op = opcode->constraints;
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op1[0] = 0;
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op2[0] = 0;
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comment1[0] = 0;
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comment2[0] = 0;
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if (opcode->insn_size > 1)
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{
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insn2 = avrdis_opcode (addr + 2, info);
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cmd_len = 4;
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}
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if (*op && *op != '?')
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{
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int regs = REGISTER_P (*op);
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avr_operand (insn, insn2, addr, *op, op1, comment1, 0);
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if (*(++op) == ',')
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avr_operand (insn, insn2, addr, *(++op), op2,
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*comment1 ? comment2 : comment1, regs);
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}
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(*prin) (stream, " %-8s", opcode->name);
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if (*op1)
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(*prin) (stream, "%s", op1);
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if (*op2)
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(*prin) (stream, ", %s", op2);
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if (*comment1)
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(*prin) (stream, "\t; %s", comment1);
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if (*comment2)
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(*prin) (stream, " %s", comment2);
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}
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else
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{
|
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switch (opcode & 0xf000)
|
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{
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case 0x0000:
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{
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reg50(opcode, rd);
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reg104(opcode, rr);
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switch (opcode & 0x0c00)
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{
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case 0x0000:
|
||||
switch (opcode & 0x0300)
|
||||
{
|
||||
case 0x0000:
|
||||
(*prin) (stream, " NOP");
|
||||
break;
|
||||
case 0x0100:
|
||||
reg_movw_d(opcode, rd);
|
||||
reg_movw_r(opcode, rr);
|
||||
(*prin) (stream, " MOVW %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0200:
|
||||
reg_muls_d(opcode, rd);
|
||||
reg_muls_r(opcode, rr);
|
||||
(*prin) (stream, " MULS %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0300:
|
||||
reg_fmul_d(opcode, rd);
|
||||
reg_fmul_r(opcode, rr);
|
||||
if (IFMASK(0x88, 0))
|
||||
(*prin) (stream, " MULSU %s,%s", rd, rr);
|
||||
else if (IFMASK(0x88, 8))
|
||||
(*prin) (stream, " FMUL %s,%s", rd, rr);
|
||||
else if (IFMASK(0x88, 0x80))
|
||||
(*prin) (stream, " FMULS %s,%s", rd, rr);
|
||||
else
|
||||
(*prin) (stream, " FMULSU %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x0400:
|
||||
(*prin) (stream, " CPC %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0800:
|
||||
(*prin) (stream, " SBC %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0c00:
|
||||
(*prin) (stream, " ADD %s,%s", rd, rr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x1000:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
reg104(opcode, rr);
|
||||
switch (opcode & 0x0c00)
|
||||
{
|
||||
case 0x0000:
|
||||
(*prin) (stream, " CPSE %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0400:
|
||||
(*prin) (stream, " CP %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0800:
|
||||
(*prin) (stream, " SUB %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0c00:
|
||||
(*prin) (stream, " ADC %s,%s", rd, rr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x2000:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
reg104(opcode, rr);
|
||||
switch (opcode & 0x0c00)
|
||||
{
|
||||
case 0x0000:
|
||||
(*prin) (stream, " AND %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0400:
|
||||
(*prin) (stream, " EOR %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0800:
|
||||
(*prin) (stream, " OR %s,%s", rd, rr);
|
||||
break;
|
||||
case 0x0c00:
|
||||
(*prin) (stream, " MOV %s,%s", rd, rr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x3000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " CPI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x4000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " SBCI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x5000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " SUBI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x6000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " ORI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x7000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " ANDI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0x9000:
|
||||
{
|
||||
switch (opcode & 0x0e00)
|
||||
{
|
||||
case 0x0000:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
switch (opcode & 0xf)
|
||||
{
|
||||
case 0x0:
|
||||
{
|
||||
(*prin) (stream, " LDS %s,0x%04X", rd,
|
||||
avrdis_opcode(addr + 2, info));
|
||||
cmd_len = 4;
|
||||
}
|
||||
break;
|
||||
case 0x1:
|
||||
(*prin) (stream, " LD %s,Z+", rd);
|
||||
break;
|
||||
case 0x2:
|
||||
(*prin) (stream, " LD %s,-Z", rd);
|
||||
break;
|
||||
case 0x4:
|
||||
(*prin) (stream, " LPM %s,Z", rd);
|
||||
break;
|
||||
case 0x5:
|
||||
(*prin) (stream, " LPM %s,Z+", rd);
|
||||
break;
|
||||
case 0x6:
|
||||
(*prin) (stream, " ELPM %s,Z", rd);
|
||||
break;
|
||||
case 0x7:
|
||||
(*prin) (stream, " ELPM %s,Z+", rd);
|
||||
break;
|
||||
case 0x9:
|
||||
(*prin) (stream, " LD %s,Y+", rd);
|
||||
break;
|
||||
case 0xa:
|
||||
(*prin) (stream, " LD %s,-Y", rd);
|
||||
break;
|
||||
case 0xc:
|
||||
(*prin) (stream, " LD %s,X", rd);
|
||||
break;
|
||||
case 0xd:
|
||||
(*prin) (stream, " LD %s,X+", rd);
|
||||
break;
|
||||
case 0xe:
|
||||
(*prin) (stream, " LD %s,-X", rd);
|
||||
break;
|
||||
case 0xf:
|
||||
(*prin) (stream, " POP %s", rd);
|
||||
break;
|
||||
default:
|
||||
(*prin) (stream, " ????");
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x0200:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
switch (opcode & 0xf)
|
||||
{
|
||||
case 0x0:
|
||||
{
|
||||
(*prin) (stream, " STS 0x%04X,%s",
|
||||
avrdis_opcode(addr + 2, info), rd);
|
||||
cmd_len = 4;
|
||||
}
|
||||
break;
|
||||
case 0x1:
|
||||
(*prin) (stream, " ST Z+,%s", rd);
|
||||
break;
|
||||
case 0x2:
|
||||
(*prin) (stream, " ST -Z,%s", rd);
|
||||
break;
|
||||
case 0x9:
|
||||
(*prin) (stream, " ST Y+,%s", rd);
|
||||
break;
|
||||
case 0xa:
|
||||
(*prin) (stream, " ST -Y,%s", rd);
|
||||
break;
|
||||
case 0xc:
|
||||
(*prin) (stream, " ST X,%s", rd);
|
||||
break;
|
||||
case 0xd:
|
||||
(*prin) (stream, " ST X+,%s", rd);
|
||||
break;
|
||||
case 0xe:
|
||||
(*prin) (stream, " ST -X,%s", rd);
|
||||
break;
|
||||
case 0xf:
|
||||
(*prin) (stream, " PUSH %s", rd);
|
||||
break;
|
||||
default:
|
||||
(*prin) (stream, " ????");
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x0400:
|
||||
{
|
||||
if (IFMASK(0x020c, 0x000c))
|
||||
{
|
||||
u32 k = ((opcode & 0x01f0) >> 3) | (opcode & 1);
|
||||
k = (k << 16) | avrdis_opcode(addr + 2, info);
|
||||
if (opcode & 0x0002)
|
||||
(*prin) (stream, " CALL 0x%06X", k*2);
|
||||
else
|
||||
(*prin) (stream, " JMP 0x%06X", k*2);
|
||||
cmd_len = 4;
|
||||
}
|
||||
else if (IFMASK(0x010f, 0x0008))
|
||||
{
|
||||
int sf = (opcode & 0x70) >> 4;
|
||||
if (opcode & 0x0080)
|
||||
(*prin) (stream, " CL%c", SREG_flags[sf]);
|
||||
else
|
||||
(*prin) (stream, " SE%c", SREG_flags[sf]);
|
||||
}
|
||||
else if (IFMASK(0x001f, 0x0009))
|
||||
{
|
||||
if (opcode & 0x0100)
|
||||
(*prin) (stream, " ICALL");
|
||||
else
|
||||
(*prin) (stream, " IJMP");
|
||||
}
|
||||
else if (IFMASK(0x001f, 0x0019))
|
||||
{
|
||||
if (opcode & 0x0100)
|
||||
(*prin) (stream, " EICALL");
|
||||
else
|
||||
(*prin) (stream, " EIJMP");
|
||||
}
|
||||
else if (IFMASK(0x010f, 0x0108))
|
||||
{
|
||||
if (IFMASK(0x0090, 0x0000))
|
||||
(*prin) (stream, " RET");
|
||||
else if (IFMASK(0x0090, 0x0010))
|
||||
(*prin) (stream, " RETI");
|
||||
else if (IFMASK(0x00e0, 0x0080))
|
||||
(*prin) (stream, " SLEEP");
|
||||
else if (IFMASK(0x00e0, 0x00a0))
|
||||
(*prin) (stream, " WDR");
|
||||
else if (IFMASK(0x00f0, 0x00c0))
|
||||
(*prin) (stream, " LPM");
|
||||
else if (IFMASK(0x00f0, 0x00d0))
|
||||
(*prin) (stream, " ELPM");
|
||||
else if (IFMASK(0x00f0, 0x00e0))
|
||||
(*prin) (stream, " SPM");
|
||||
else if (IFMASK(0x00f0, 0x00f0))
|
||||
(*prin) (stream, " ESPM");
|
||||
else
|
||||
(*prin) (stream, " ????");
|
||||
}
|
||||
else
|
||||
{
|
||||
const char* p;
|
||||
reg50(opcode, rd);
|
||||
p = sect94[opcode & 0xf];
|
||||
if (!p)
|
||||
p = "????";
|
||||
(*prin) (stream, " %-8s%s", p, rd);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x0600:
|
||||
{
|
||||
if (opcode & 0x0200)
|
||||
{
|
||||
lit204(opcode, rd);
|
||||
reg20w(opcode, rr);
|
||||
if (opcode & 0x0100)
|
||||
(*prin) (stream, " SBIW %s,%s", rr, rd);
|
||||
else
|
||||
(*prin) (stream, " ADIW %s,%s", rr, rd);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0x0800:
|
||||
case 0x0a00:
|
||||
{
|
||||
(*prin) (stream, " %-8s0x%02X,%d",
|
||||
sect98[(opcode & 0x0300) >> 8],
|
||||
(opcode & 0xf8) >> 3,
|
||||
opcode & 7);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
reg104(opcode, rr);
|
||||
(*prin) (stream, " MUL %s,%s", rd, rr);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0xb000:
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
regPP(opcode, rr);
|
||||
if (opcode & 0x0800)
|
||||
(*prin) (stream, " OUT %s,%s", rr, rd);
|
||||
else
|
||||
(*prin) (stream, " IN %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0xc000:
|
||||
{
|
||||
add0fff(opcode, rd, addr);
|
||||
(*prin) (stream, " RJMP %s", rd);
|
||||
}
|
||||
break;
|
||||
case 0xd000:
|
||||
{
|
||||
add0fff(opcode, rd, addr);
|
||||
(*prin) (stream, " RCALL %s", rd);
|
||||
}
|
||||
break;
|
||||
case 0xe000:
|
||||
{
|
||||
reg40(opcode, rd);
|
||||
lit404(opcode, rr);
|
||||
(*prin) (stream, " LDI %s,%s", rd, rr);
|
||||
}
|
||||
break;
|
||||
case 0xf000:
|
||||
{
|
||||
if (opcode & 0x0800)
|
||||
{
|
||||
reg50(opcode, rd);
|
||||
(*prin) (stream, " %-8s%s,%d",
|
||||
last4[(opcode & 0x0600) >> 9],
|
||||
rd, opcode & 7);
|
||||
}
|
||||
else
|
||||
{
|
||||
char* p;
|
||||
add03f8(opcode, rd, addr);
|
||||
p = branchs[((opcode & 0x0400) >> 7) | (opcode & 7)];
|
||||
(*prin) (stream, " %-8s%s", p, rd);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
(*prin) (stream, ".word 0x%04x\t; ????", insn);
|
||||
|
||||
return cmd_len;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue