[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.
bfd/ * elfxx-mips.c (infer_mips_abiflags): Use ases instead of isa_ext for infer ABI flags. (print_mips_ases): Add Loongson EXT extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT extension. elfcpp/ * mips.h (AFL_ASE_LOONGSON_EXT): New enum. gas/ * NEWS: Mention Loongson EXTensions (EXT) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and OPTION_NO_LOONGSON_EXT. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to AFL_ASE_LOONGSON_EXT. (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a. (md_show_usage): Add help for -mloongson-ext and -mno-loongson-ext. * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext. * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext, .set loongson-ext and .set noloongson-ext. * testsuite/gas/mips/loongson-mmi.d: Add ASE flag. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT. * opcode/mips.h (ASE_LOONGSON_EXT): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (IL3A): Delete. * mips-opc.c (LEXT): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT instructions.
This commit is contained in:
Chenghua Xu
parent
716c08de28
commit
bdc6c06e3b
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@ -1,3 +1,9 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elfxx-mips.c (infer_mips_abiflags): Use ases instead of
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isa_ext for infer ABI flags.
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(print_mips_ases): Add Loongson EXT extension.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elfxx-mips.c (print_mips_ases): Add CAM extension.
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@ -14250,7 +14250,7 @@ infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags)
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&& abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT
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&& abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A
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&& abiflags->isa_level >= 32
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&& abiflags->isa_ext != AFL_EXT_LOONGSON_3A)
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&& abiflags->ases != AFL_ASE_LOONGSON_EXT)
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abiflags->flags1 |= AFL_FLAGS1_ODDSPREG;
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}
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@ -15679,6 +15679,8 @@ print_mips_ases (FILE *file, unsigned int mask)
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fputs ("\n\tLoongson MMI ASE", file);
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if (mask & AFL_ASE_LOONGSON_CAM)
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fputs ("\n\tLoongson CAM ASE", file);
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if (mask & AFL_ASE_LOONGSON_EXT)
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fputs ("\n\tLoongson EXT ASE", file);
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if (mask == 0)
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fprintf (file, "\n\t%s", _("None"));
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else if ((mask & ~AFL_ASE_MASK) != 0)
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* readelf.c (print_mips_ases): Add Loongson EXT extension.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* readelf.c (print_mips_ases): Add CAM extension.
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@ -15653,6 +15653,8 @@ print_mips_ases (unsigned int mask)
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fputs ("\n\tLoongson MMI ASE", stdout);
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if (mask & AFL_ASE_LOONGSON_CAM)
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fputs ("\n\tLoongson CAM ASE", stdout);
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if (mask & AFL_ASE_LOONGSON_EXT)
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fputs ("\n\tLoongson EXT ASE", stdout);
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if (mask == 0)
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fprintf (stdout, "\n\t%s", _("None"));
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else if ((mask & ~AFL_ASE_MASK) != 0)
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips.h (AFL_ASE_LOONGSON_EXT): New enum.
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2018-07-06 Alan Modra <amodra@gmail.com>
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* powerpc.h (Tag_GNU_Power_ABI_FP): Define.
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@ -308,7 +308,9 @@ enum
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// MICROMIPS ASE.
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AFL_ASE_MICROMIPS = 0x00000800,
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// XPA ASE.
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AFL_ASE_XPA = 0x00001000
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AFL_ASE_XPA = 0x00001000,
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// Loongson EXT ASE.
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AFL_ASE_LOONGSON_EXT = 0x00002000
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};
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// Values for the isa_ext word of an ABI flags structure.
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@ -1,3 +1,20 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* NEWS: Mention Loongson EXTensions (EXT) support.
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* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
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OPTION_NO_LOONGSON_EXT.
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(md_longopts): Likewise.
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(mips_ases): Define availability for EXT.
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(mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
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AFL_ASE_LOONGSON_EXT.
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(mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
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(md_show_usage): Add help for -mloongson-ext and
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-mno-loongson-ext.
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* doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
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* doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
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.set loongson-ext and .set noloongson-ext.
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* testsuite/gas/mips/loongson-mmi.d: Add ASE flag.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* NEWS: Mention Loongson Content Address Memory (CAM)
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2
gas/NEWS
2
gas/NEWS
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@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for the MIPS Loongson EXTensions (EXT) instructions.
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* Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
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* Add support for the C-SKY processor series.
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@ -1533,6 +1533,8 @@ enum options
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OPTION_NO_LOONGSON_MMI,
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OPTION_LOONGSON_CAM,
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OPTION_NO_LOONGSON_CAM,
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OPTION_LOONGSON_EXT,
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OPTION_NO_LOONGSON_EXT,
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OPTION_END_OF_ENUM
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};
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@ -1597,6 +1599,8 @@ struct option md_longopts[] =
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{"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
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{"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
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{"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
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{"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
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{"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
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/* Old-style architecture options. Don't add more of these. */
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{"m4650", no_argument, NULL, OPTION_M4650},
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@ -1804,6 +1808,11 @@ static const struct mips_ase mips_ases[] = {
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OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
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0, 0, -1, -1,
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-1 },
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{ "loongson-ext", ASE_LOONGSON_EXT, 0,
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OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
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0, 0, -1, -1,
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-1 },
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};
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/* The set of ASEs that require -mfp64. */
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@ -19039,6 +19048,8 @@ mips_convert_ase_flags (int ase)
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ext_ases |= AFL_ASE_LOONGSON_MMI;
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if (ase & ASE_LOONGSON_CAM)
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ext_ases |= AFL_ASE_LOONGSON_CAM;
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if (ase & ASE_LOONGSON_EXT)
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ext_ases |= AFL_ASE_LOONGSON_EXT;
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return ext_ases;
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}
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@ -19786,8 +19797,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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/* MIPS 64 Release 2 */
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/* Loongson CPU core */
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{ "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM, ISA_MIPS64R2,
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CPU_LOONGSON_3A },
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{ "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
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ISA_MIPS64R2, CPU_LOONGSON_3A },
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/* Cavium Networks Octeon CPU core */
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{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
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@ -20066,6 +20077,9 @@ MIPS options:\n\
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-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
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-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
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fprintf (stream, _("\
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-mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
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-mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
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fprintf (stream, _("\
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-minsn32 only generate 32-bit microMIPS instructions\n\
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-mno-insn32 generate all microMIPS instructions\n"));
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fprintf (stream, _("\
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@ -446,6 +446,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mginv}] [@b{-mno-ginv}]
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[@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
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[@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
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[@b{-mloongson-ext}] [@b{-mno-loongson-ext}]
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[@b{-minsn32}] [@b{-mno-insn32}]
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[@b{-mfix7000}] [@b{-mno-fix7000}]
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[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
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@ -1580,6 +1581,12 @@ Generate code for the Loongson Content Address Memory (CAM) instructions.
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This tells the assembler to accept Loongson CAM instructions.
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@samp{-mno-loongson-cam} turns off this option.
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@item -mloongson-ext
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@itemx -mno-loongson-ext
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Generate code for the Loongson EXTensions (EXT) instructions.
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This tells the assembler to accept Loongson EXT instructions.
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@samp{-mno-loongson-ext} turns off this option.
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@item -minsn32
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@itemx -mno-insn32
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Only use 32-bit instruction encodings when generating code for the
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@ -260,6 +260,13 @@ Application Specific Extension. This tells the assembler to accept CAM
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instructions.
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@samp{-mno-loongson-cam} turns off this option.
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@item -mloongson-ext
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@itemx -mno-loongson-ext
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Generate code for the Loongson EXTensions (EXT) instructions
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Application Specific Extension. This tells the assembler to accept EXT
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instructions.
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@samp{-mno-loongson-ext} turns off this option.
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@item -minsn32
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@itemx -mno-insn32
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Only use 32-bit instruction encodings when generating code for the
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@ -1167,6 +1174,14 @@ instructions from the Loongson CAM from that point on in the assembly.
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The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
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from being accepted.
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@cindex Loongson EXTensions (EXT) instructions generation override
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@kindex @code{.set loongson-ext}
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@kindex @code{.set noloongson-ext}
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The directive @code{.set loongson-ext} makes the assembler accept
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instructions from the Loongson EXT from that point on in the assembly.
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The @code{.set noloongson-ext} directive prevents Loongson EXT instructions
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from being accepted.
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Traditional MIPS assemblers do not support these directives.
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@node MIPS Floating-Point
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@ -16,6 +16,7 @@ ISA Extension: Loongson 3A
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ASEs:
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Loongson MMI ASE
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Loongson CAM ASE
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Loongson EXT ASE
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FLAGS 1: .*
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FLAGS 2: .*
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@ -1,3 +1,9 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
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* opcode/mips.h (ASE_LOONGSON_EXT): New macro.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
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@ -1240,7 +1240,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
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#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */
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#define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE. */
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#define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE. */
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#define AFL_ASE_MASK 0x000effff /* All ASEs. */
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#define AFL_ASE_LOONGSON_EXT 0x00100000 /* Loongson EXT instructions. */
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#define AFL_ASE_MASK 0x001effff /* All ASEs. */
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/* Values for the isa_ext word of an ABI flags structure. */
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@ -1306,6 +1306,8 @@ static const unsigned int mips_isa_table[] = {
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#define ASE_LOONGSON_MMI 0x00200000
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/* Loongson Content Address Memory (CAM). */
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#define ASE_LOONGSON_CAM 0x00400000
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/* Loongson EXTensions (EXT) instructions. */
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#define ASE_LOONGSON_EXT 0x00800000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -1,3 +1,14 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Add EXT to loongson3a
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descriptors.
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(parse_mips_ase_option): Handle -M loongson-ext option.
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(print_mips_disassembler_options): Document -M loongson-ext.
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* mips-opc.c (IL3A): Delete.
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* mips-opc.c (LEXT): New macro.
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(mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
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instructions.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
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@ -630,7 +630,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
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{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
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ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,
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ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
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mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
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mips_hwr_names_numeric },
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@ -948,6 +948,12 @@ parse_mips_ase_option (const char *option)
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return TRUE;
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}
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if (CONST_STRNEQ (option, "loongson-ext"))
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{
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mips_ase |= ASE_LOONGSON_EXT;
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return TRUE;
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}
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return FALSE;
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}
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@ -2603,6 +2609,10 @@ static struct
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N_("Recognize the Loongson Content Address Memory (CAM) "
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" instructions.\n"),
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MIPS_OPTION_ARG_NONE },
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{ "loongson-ext",
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N_("Recognize the Loongson EXTensions (EXT) "
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" instructions.\n"),
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MIPS_OPTION_ARG_NONE },
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{ "gpr-names=", N_("Print GPR names according to specified ABI.\n\
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Default: based on binary being disassembled.\n"),
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MIPS_OPTION_ARG_ABI },
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@ -308,7 +308,6 @@ decode_mips_operand (const char *p)
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#define IL2E (INSN_LOONGSON_2E)
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#define IL2F (INSN_LOONGSON_2F)
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#define IL3A (INSN_LOONGSON_3A)
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#define P3 INSN_4650
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#define L1 INSN_4010
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@ -418,6 +417,9 @@ decode_mips_operand (const char *p)
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/* Loongson Content Address Memory (CAM) support. */
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#define LCAM ASE_LOONGSON_CAM
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/* Loongson EXTensions (EXT) instructions support. */
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#define LEXT ASE_LOONGSON_EXT
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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for arguments must apear in the correct order in this table for the
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@ -466,56 +468,56 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
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{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 },
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{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
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{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
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{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
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{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
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{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
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{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
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{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 },
|
||||
{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 },
|
||||
{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
|
||||
{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
|
||||
{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
|
||||
{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
|
||||
{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
|
||||
{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
|
||||
|
||||
/* R5900 VU0 Macromode instructions. */
|
||||
{"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
|
|
@ -1442,7 +1444,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 },
|
||||
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 },
|
||||
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 },
|
||||
{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F|IL3A, 0, 0 },
|
||||
{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 },
|
||||
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 },
|
||||
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 },
|
||||
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
|
||||
|
|
@ -2441,40 +2443,40 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
/* ST Microelectronics Loongson-2E and -2F. */
|
||||
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 },
|
||||
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 },
|
||||
{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, LEXT, 0 },
|
||||
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
|
||||
{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
|
||||
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue