[AArch64, Binutils] Add missing TSB instruction
This patch implements the TSB instructions: https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/ tsb-csync-trace-synchronization-barrier Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the "hint" version. The operand checker part still uses the existing infratructure for AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly. gas/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_barrier_psb): Update error messages to include TSB. * testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests. * testsuite/gas/aarch64/system-2.s: Add new tsb tests. * testsuite/gas/aarch64/system.d: Update. opcodes/ChangeLog: 2020-04-20 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_none): New. * aarch64-asm.h (ins_none): New declaration. * aarch64-dis.c (aarch64_ext_none): New. * aarch64-dis.h (ext_none): New declaration. * aarch64-opc.c (aarch64_print_operand): Update case for AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_opcode_table): Add tsb. (AARCH64_OPERANDS): Update inserter/extracter for AARCH64_OPND_BARRIER_PSB to use new dummy functions. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
This commit is contained in:
Sudakshina Das
parent
8a6e1d1d7f
commit
c2e5c986b3
@ -1,3 +1,11 @@
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_barrier_psb): Update error messages
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to include TSB.
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* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
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* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
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* testsuite/gas/aarch64/system.d: Update.
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/bti.d: Update -march option.
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@ -4026,7 +4026,7 @@ parse_barrier_psb (char **str,
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if (!o)
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{
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set_fatal_syntax_error
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( _("unknown or missing option to PSB"));
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( _("unknown or missing option to PSB/TSB"));
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return PARSE_FAIL;
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}
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@ -4034,7 +4034,7 @@ parse_barrier_psb (char **str,
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{
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/* PSB only accepts option name 'CSYNC'. */
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set_syntax_error
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(_("the specified option is not accepted for PSB"));
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(_("the specified option is not accepted for PSB/TSB"));
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return PARSE_FAIL;
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}
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@ -1,4 +1,4 @@
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#as: -march=armv8.2-a+profile
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#as: -march=armv8-a
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#objdump: -dr
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.*: file format .*
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@ -6,8 +6,11 @@
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Disassembly of section \.text:
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0+ <.*>:
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0: d503221f esb
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4: d503221f esb
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8: d503223f psb csync
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c: d503223f psb csync
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10: d503223f psb csync
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.*: d503221f esb
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.*: d503221f esb
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.*: d503223f psb csync
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.*: d503223f psb csync
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.*: d503223f psb csync
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.*: d503225f tsb csync
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.*: d503225f tsb csync
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.*: d503225f tsb csync
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@ -9,3 +9,8 @@
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psb csync
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psb CSYNC
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hint #0x11
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/* Trace sync barrier. */
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tsb csync
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tsb CSYNC
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hint #0x12
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@ -30,7 +30,7 @@ Disassembly of section \.text:
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.*: d50321ff hint #0xf
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.*: d503221f (hint #0x10|esb)
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.*: d503223f (hint #0x11|psb csync)
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.*: d503225f hint #0x12
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.*: d503225f (hint #0x12|tsb csync)
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.*: d503227f hint #0x13
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.*: d503229f (hint #0x14|csdb)
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.*: d50322bf hint #0x15
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@ -1,3 +1,18 @@
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm.c (aarch64_ins_none): New.
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* aarch64-asm.h (ins_none): New declaration.
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* aarch64-dis.c (aarch64_ext_none): New.
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* aarch64-dis.h (ext_none): New declaration.
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* aarch64-opc.c (aarch64_print_operand): Update case for
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AARCH64_OPND_BARRIER_PSB.
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* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
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(AARCH64_OPERANDS): Update inserter/extracter for
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AARCH64_OPND_BARRIER_PSB to use new dummy functions.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2020-04-20 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
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@ -426,14 +426,15 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1183: /* movz */
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value = 1183; /* --> movz. */
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break;
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case 1236: /* autibsp */
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case 1235: /* autibz */
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case 1234: /* autiasp */
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case 1233: /* autiaz */
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case 1232: /* pacibsp */
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case 1231: /* pacibz */
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case 1230: /* paciasp */
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case 1229: /* paciaz */
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case 1237: /* autibsp */
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case 1236: /* autibz */
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case 1235: /* autiasp */
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case 1234: /* autiaz */
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case 1233: /* pacibsp */
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case 1232: /* pacibz */
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case 1231: /* paciasp */
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case 1230: /* paciaz */
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case 1210: /* tsb */
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case 1209: /* psb */
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case 1208: /* esb */
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case 1207: /* autib1716 */
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@ -452,140 +453,140 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1193: /* hint */
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value = 1193; /* --> hint. */
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break;
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case 1213: /* pssbb */
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case 1212: /* ssbb */
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case 1211: /* dsb */
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value = 1211; /* --> dsb. */
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case 1214: /* pssbb */
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case 1213: /* ssbb */
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case 1212: /* dsb */
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value = 1212; /* --> dsb. */
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break;
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case 1224: /* cpp */
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case 1223: /* dvp */
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case 1222: /* cfp */
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case 1221: /* tlbi */
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case 1220: /* ic */
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case 1219: /* dc */
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case 1218: /* at */
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case 1217: /* sys */
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value = 1217; /* --> sys. */
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case 1225: /* cpp */
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case 1224: /* dvp */
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case 1223: /* cfp */
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case 1222: /* tlbi */
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case 1221: /* ic */
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case 1220: /* dc */
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case 1219: /* at */
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case 1218: /* sys */
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value = 1218; /* --> sys. */
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break;
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case 2034: /* bic */
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case 1284: /* and */
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value = 1284; /* --> and. */
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case 2035: /* bic */
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case 1285: /* and */
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value = 1285; /* --> and. */
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break;
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case 1267: /* mov */
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case 1286: /* and */
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value = 1286; /* --> and. */
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case 1268: /* mov */
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case 1287: /* and */
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value = 1287; /* --> and. */
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break;
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case 1271: /* movs */
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case 1287: /* ands */
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value = 1287; /* --> ands. */
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case 1272: /* movs */
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case 1288: /* ands */
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value = 1288; /* --> ands. */
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break;
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case 2035: /* cmple */
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case 1322: /* cmpge */
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value = 1322; /* --> cmpge. */
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case 2036: /* cmple */
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case 1323: /* cmpge */
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value = 1323; /* --> cmpge. */
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break;
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case 2038: /* cmplt */
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case 1325: /* cmpgt */
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value = 1325; /* --> cmpgt. */
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case 2039: /* cmplt */
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case 1326: /* cmpgt */
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value = 1326; /* --> cmpgt. */
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break;
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case 2036: /* cmplo */
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case 1327: /* cmphi */
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value = 1327; /* --> cmphi. */
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case 2037: /* cmplo */
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case 1328: /* cmphi */
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value = 1328; /* --> cmphi. */
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break;
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case 2037: /* cmpls */
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case 1330: /* cmphs */
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value = 1330; /* --> cmphs. */
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case 2038: /* cmpls */
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case 1331: /* cmphs */
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value = 1331; /* --> cmphs. */
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break;
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case 1264: /* mov */
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case 1352: /* cpy */
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value = 1352; /* --> cpy. */
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break;
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case 1266: /* mov */
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case 1265: /* mov */
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case 1353: /* cpy */
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value = 1353; /* --> cpy. */
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break;
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case 2045: /* fmov */
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case 1269: /* mov */
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case 1267: /* mov */
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case 1354: /* cpy */
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value = 1354; /* --> cpy. */
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break;
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case 1259: /* mov */
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case 1366: /* dup */
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value = 1366; /* --> dup. */
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case 2046: /* fmov */
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case 1270: /* mov */
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case 1355: /* cpy */
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value = 1355; /* --> cpy. */
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break;
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case 1261: /* mov */
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case 1258: /* mov */
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case 1260: /* mov */
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case 1367: /* dup */
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value = 1367; /* --> dup. */
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break;
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case 2044: /* fmov */
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case 1263: /* mov */
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case 1262: /* mov */
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case 1259: /* mov */
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case 1368: /* dup */
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value = 1368; /* --> dup. */
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break;
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case 1262: /* mov */
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case 1369: /* dupm */
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value = 1369; /* --> dupm. */
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case 2045: /* fmov */
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case 1264: /* mov */
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case 1369: /* dup */
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value = 1369; /* --> dup. */
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break;
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case 2039: /* eon */
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case 1371: /* eor */
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value = 1371; /* --> eor. */
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case 1263: /* mov */
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case 1370: /* dupm */
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value = 1370; /* --> dupm. */
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break;
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case 1272: /* not */
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case 1373: /* eor */
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value = 1373; /* --> eor. */
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case 2040: /* eon */
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case 1372: /* eor */
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value = 1372; /* --> eor. */
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break;
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case 1273: /* nots */
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case 1374: /* eors */
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value = 1374; /* --> eors. */
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case 1273: /* not */
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case 1374: /* eor */
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value = 1374; /* --> eor. */
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break;
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case 2040: /* facle */
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case 1379: /* facge */
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value = 1379; /* --> facge. */
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case 1274: /* nots */
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case 1375: /* eors */
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value = 1375; /* --> eors. */
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break;
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case 2041: /* faclt */
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case 1380: /* facgt */
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value = 1380; /* --> facgt. */
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case 2041: /* facle */
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case 1380: /* facge */
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value = 1380; /* --> facge. */
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break;
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case 2042: /* fcmle */
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case 1393: /* fcmge */
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value = 1393; /* --> fcmge. */
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case 2042: /* faclt */
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case 1381: /* facgt */
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value = 1381; /* --> facgt. */
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break;
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case 2043: /* fcmlt */
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case 1395: /* fcmgt */
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value = 1395; /* --> fcmgt. */
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case 2043: /* fcmle */
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case 1394: /* fcmge */
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value = 1394; /* --> fcmge. */
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break;
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case 2044: /* fcmlt */
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case 1396: /* fcmgt */
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value = 1396; /* --> fcmgt. */
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break;
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case 1257: /* fmov */
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case 1402: /* fcpy */
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value = 1402; /* --> fcpy. */
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break;
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case 1256: /* fmov */
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case 1401: /* fcpy */
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value = 1401; /* --> fcpy. */
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case 1425: /* fdup */
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value = 1425; /* --> fdup. */
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break;
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case 1255: /* fmov */
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case 1424: /* fdup */
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value = 1424; /* --> fdup. */
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break;
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case 1257: /* mov */
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case 1755: /* orr */
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value = 1755; /* --> orr. */
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break;
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case 2046: /* orn */
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case 1258: /* mov */
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case 1756: /* orr */
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value = 1756; /* --> orr. */
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break;
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case 1260: /* mov */
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case 1758: /* orr */
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value = 1758; /* --> orr. */
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case 2047: /* orn */
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case 1757: /* orr */
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value = 1757; /* --> orr. */
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break;
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case 1270: /* movs */
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case 1759: /* orrs */
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value = 1759; /* --> orrs. */
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case 1261: /* mov */
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case 1759: /* orr */
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value = 1759; /* --> orr. */
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break;
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case 1265: /* mov */
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case 1821: /* sel */
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value = 1821; /* --> sel. */
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case 1271: /* movs */
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case 1760: /* orrs */
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value = 1760; /* --> orrs. */
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break;
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case 1268: /* mov */
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case 1266: /* mov */
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case 1822: /* sel */
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value = 1822; /* --> sel. */
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break;
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case 1269: /* mov */
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case 1823: /* sel */
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value = 1823; /* --> sel. */
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break;
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default: return NULL;
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}
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@ -771,6 +772,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 104:
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return aarch64_ins_prfop (self, info, code, inst, errors);
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case 105:
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return aarch64_ins_none (self, info, code, inst, errors);
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case 106:
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return aarch64_ins_hint (self, info, code, inst, errors);
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case 107:
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@ -78,6 +78,17 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
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/* Operand inserters. */
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/* Insert nothing. */
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bfd_boolean
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aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
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const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
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aarch64_insn *code ATTRIBUTE_UNUSED,
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const aarch64_inst *inst ATTRIBUTE_UNUSED,
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aarch64_operand_error *errors ATTRIBUTE_UNUSED)
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{
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return TRUE;
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}
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/* Insert register number. */
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bfd_boolean
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aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
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@ -42,6 +42,7 @@ bfd_boolean aarch64_insert_operand (const aarch64_operand *,
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aarch64_insn *, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_INSERTER (ins_none);
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AARCH64_DECL_OPD_INSERTER (ins_regno);
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AARCH64_DECL_OPD_INSERTER (ins_reglane);
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AARCH64_DECL_OPD_INSERTER (ins_reglist);
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File diff suppressed because it is too large
Load Diff
@ -251,6 +251,16 @@ get_expected_qualifier (const aarch64_inst *inst, int i)
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/* Operand extractors. */
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bfd_boolean
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aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
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aarch64_opnd_info *info ATTRIBUTE_UNUSED,
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const aarch64_insn code ATTRIBUTE_UNUSED,
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const aarch64_inst *inst ATTRIBUTE_UNUSED,
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aarch64_operand_error *errors ATTRIBUTE_UNUSED)
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{
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return TRUE;
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}
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bfd_boolean
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aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
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const aarch64_insn code,
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@ -62,6 +62,7 @@ aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
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const aarch64_insn, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_EXTRACTOR (ext_none);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
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@ -129,7 +129,7 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 32"},
|
||||
@ -309,17 +309,17 @@ static const unsigned op_enum_table [] =
|
||||
391,
|
||||
413,
|
||||
415,
|
||||
1260,
|
||||
1265,
|
||||
1258,
|
||||
1257,
|
||||
1261,
|
||||
1268,
|
||||
1270,
|
||||
1266,
|
||||
1259,
|
||||
1258,
|
||||
1262,
|
||||
1269,
|
||||
1271,
|
||||
1267,
|
||||
1273,
|
||||
1272,
|
||||
1268,
|
||||
1274,
|
||||
1273,
|
||||
131,
|
||||
};
|
||||
|
||||
|
||||
@ -3762,6 +3762,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_BARRIER_PSB:
|
||||
snprintf (buf, size, "csync");
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_BTI_TARGET:
|
||||
if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
|
||||
snprintf (buf, size, "%s", opnd->hint_option->name);
|
||||
|
||||
@ -3841,6 +3841,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
|
||||
CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
|
||||
CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
|
||||
CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
|
||||
CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
|
||||
@ -5314,8 +5315,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"the ISB option name SY or an optional 4-bit unsigned immediate") \
|
||||
Y(SYSTEM, prfop, "PRFOP", 0, F(), \
|
||||
"a prefetch operation specifier") \
|
||||
Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
|
||||
"the PSB option name CSYNC") \
|
||||
Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \
|
||||
"the PSB/TSB option name CSYNC") \
|
||||
Y(SYSTEM, hint, "BTI", 0, F (), \
|
||||
"BTI targets j/c/jc") \
|
||||
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user