[PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (print_insn_thumb32): Handle new instructions.
This commit is contained in:
parent
ed63aa178c
commit
d052b9b7cb
|
@ -1,3 +1,9 @@
|
||||||
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||||||
|
Michael Collison <michael.collison@arm.com>
|
||||||
|
|
||||||
|
* arm-dis.c (thumb32_opcodes): Add new instructions.
|
||||||
|
(print_insn_thumb32): Handle new instructions.
|
||||||
|
|
||||||
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||||||
Michael Collison <michael.collison@arm.com>
|
Michael Collison <michael.collison@arm.com>
|
||||||
|
|
||||||
|
|
|
@ -3949,13 +3949,21 @@ static const struct opcode32 thumb32_opcodes[] =
|
||||||
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
|
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
|
||||||
instructions. */
|
instructions. */
|
||||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
|
0xf00fe001, 0xffffffff, "lctp%c"},
|
||||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
|
||||||
0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
|
|
||||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
0xf02fc001, 0xfffff001, "le\t%P"},
|
0xf02fc001, 0xfffff001, "le\t%P"},
|
||||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
0xf00fc001, 0xfffff001, "le\tlr, %P"},
|
0xf00fc001, 0xfffff001, "le\tlr, %P"},
|
||||||
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
|
0xf01fc001, 0xfffff001, "letp\tlr, %P"},
|
||||||
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
|
0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
|
||||||
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
|
0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
|
||||||
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
|
0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
|
||||||
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
|
0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
|
||||||
|
|
||||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
|
||||||
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
|
0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
|
||||||
|
@ -10171,6 +10179,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
||||||
|
|
||||||
switch (*c)
|
switch (*c)
|
||||||
{
|
{
|
||||||
|
case 's':
|
||||||
|
if (val <= 3)
|
||||||
|
func (stream, "%s", mve_vec_sizename[val]);
|
||||||
|
else
|
||||||
|
func (stream, "<undef size>");
|
||||||
|
break;
|
||||||
|
|
||||||
case 'd':
|
case 'd':
|
||||||
func (stream, "%lu", val);
|
func (stream, "%lu", val);
|
||||||
value_in_comment = val;
|
value_in_comment = val;
|
||||||
|
|
Loading…
Reference in New Issue