[PATCH 50/57][Arm][OBJDUMP] Add support for MVE shift instructions
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_mve_shift_n): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
parent
897b9bbcff
commit
ed63aa178c
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@ -1,3 +1,16 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_undefined): Add new reasons.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_size): Likewise.
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(print_mve_shift_n): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -184,6 +184,30 @@ enum mve_instructions
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MVE_VHCADD,
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MVE_VCMLA_FP,
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MVE_VCMUL_FP,
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MVE_VQRSHL_T1,
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MVE_VQRSHL_T2,
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MVE_VQRSHRN,
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MVE_VQRSHRUN,
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MVE_VQSHL_T1,
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MVE_VQSHL_T2,
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MVE_VQSHLU_T3,
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MVE_VQSHL_T4,
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MVE_VQSHRN,
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MVE_VQSHRUN,
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MVE_VRSHL_T1,
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MVE_VRSHL_T2,
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MVE_VRSHR,
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MVE_VRSHRN,
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MVE_VSHL_T1,
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MVE_VSHL_T2,
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MVE_VSHL_T3,
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MVE_VSHLC,
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MVE_VSHLL_T1,
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MVE_VSHLL_T2,
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MVE_VSHR,
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MVE_VSHRN,
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MVE_VSLI,
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MVE_VSRI,
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MVE_NONE
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};
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@ -216,6 +240,7 @@ enum mve_unpredictable
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enum mve_undefined
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{
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UNDEF_SIZE, /* undefined size. */
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UNDEF_SIZE_0, /* undefined because size == 0. */
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UNDEF_SIZE_2, /* undefined because size == 2. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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@ -2420,6 +2445,63 @@ static const struct mopcode32 mve_opcodes[] =
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0xef800050, 0xefb810f0,
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"vorr%v.i%8-11s\t%13-15,22Q, %E"},
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/* Vector VQSHL T2 Variant.
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NOTE: MVE_VQSHL_T2 must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHL_T2,
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0xef800750, 0xef801fd1,
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"vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VQSHLU T3 Variant
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NOTE: MVE_VQSHL_T2 must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHLU_T3,
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0xff800650, 0xff801fd1,
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"vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VRSHR
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NOTE: MVE_VRSHR must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRSHR,
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0xef800250, 0xef801fd1,
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"vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSHL.
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NOTE: MVE_VSHL must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHL_T1,
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0xef800550, 0xff801fd1,
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"vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSHR
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NOTE: MVE_VSHR must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHR,
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0xef800050, 0xef801fd1,
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"vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSLI
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NOTE: MVE_VSLI must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSLI,
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0xff800550, 0xff801fd1,
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"vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSRI
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NOTE: MVE_VSRI must appear in the table before
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSRI,
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0xff800450, 0xff801fd1,
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"vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VMOV immediate to vector,
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cmode == 11x1 -> VMVN which is UNDEFINED
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for such a cmode. */
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@ -2462,6 +2544,13 @@ static const struct mopcode32 mve_opcodes[] =
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0xee100b10, 0xff100f1f,
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"vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
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/* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
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to instruction opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHLL_T1,
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0xeea00f40, 0xefa00fd1,
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"vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VMOVL long. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOVL,
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@ -2612,6 +2701,54 @@ static const struct mopcode32 mve_opcodes[] =
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0xfe010e60, 0xff811f70,
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"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQRSHL T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRSHL_T1,
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0xef000550, 0xef811f51,
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"vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
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/* Vector VQRSHL T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRSHL_T2,
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0xee331ee0, 0xefb31ff0,
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"vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
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/* Vector VQRSHRN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRSHRN,
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0xee800f41, 0xefa00fd1,
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"vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VQRSHRUN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRSHRUN,
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0xfe800fc0, 0xffa00fd1,
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"vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VQSHL T1 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHL_T1,
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0xee311ee0, 0xefb31ff0,
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"vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
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/* Vector VQSHL T4 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHL_T4,
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0xef000450, 0xef811f51,
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"vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
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/* Vector VQSHRN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHRN,
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0xee800f40, 0xefa00fd1,
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"vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VQSHRUN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQSHRUN,
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0xee800fc0, 0xffa00fd1,
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"vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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@ -2630,6 +2767,54 @@ static const struct mopcode32 mve_opcodes[] =
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0xee801f00, 0xef811f51,
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"vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VRSHL T1 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRSHL_T1,
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0xef000540, 0xef811f51,
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"vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
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/* Vector VRSHL T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRSHL_T2,
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0xee331e60, 0xefb31ff0,
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"vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
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/* Vector VRSHRN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRSHRN,
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0xfe800fc1, 0xffa00fd1,
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"vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSHL T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHL_T2,
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0xee311e60, 0xefb31ff0,
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"vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
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/* Vector VSHL T3 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHL_T3,
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0xef000440, 0xef811f51,
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"vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
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/* Vector VSHLC. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHLC,
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0xeea00fc0, 0xffa01ff0,
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"vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
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/* Vector VSHLL T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHLL_T2,
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0xee310e01, 0xefb30fd1,
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"vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
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/* Vector VSHRN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHRN,
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0xee800fc1, 0xffa00fd1,
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"vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VST2 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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@ -4734,6 +4919,10 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VQRSHL_T1:
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case MVE_VQSHL_T4:
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case MVE_VRSHL_T1:
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case MVE_VSHL_T3:
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case MVE_VCADD_VEC:
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case MVE_VHCADD:
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case MVE_VDDUP:
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@ -4841,6 +5030,11 @@ is_mve_encoding_conflict (unsigned long given,
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return FALSE;
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}
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case MVE_VQRSHL_T2:
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case MVE_VQSHL_T1:
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case MVE_VRSHL_T2:
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case MVE_VSHL_T2:
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case MVE_VSHLL_T2:
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case MVE_VADDV:
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case MVE_VMOVN:
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case MVE_VQMOVUN:
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@ -4873,6 +5067,32 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VSHLL_T1:
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if (arm_decode_field (given, 16, 18) == 0)
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{
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unsigned long sz = arm_decode_field (given, 19, 20);
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if ((sz == 1) || (sz == 2))
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return TRUE;
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else
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return FALSE;
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}
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else
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return FALSE;
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case MVE_VQSHL_T2:
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case MVE_VQSHLU_T3:
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case MVE_VRSHR:
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case MVE_VSHL_T1:
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case MVE_VSHR:
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case MVE_VSLI:
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case MVE_VSRI:
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if (arm_decode_field (given, 19, 21) == 0)
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return TRUE;
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else
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return FALSE;
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default:
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return FALSE;
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@ -5228,6 +5448,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VSHLL_T2:
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case MVE_VMOVN:
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if (arm_decode_field (given, 18, 19) == 2)
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{
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@ -5250,6 +5471,56 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VQSHRN:
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case MVE_VQSHRUN:
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case MVE_VSHLL_T1:
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case MVE_VSHRN:
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{
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unsigned long sz = arm_decode_field (given, 19, 20);
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if (sz == 1)
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return FALSE;
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else if ((sz & 2) == 2)
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return FALSE;
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else
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{
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*undefined_code = UNDEF_SIZE;
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return TRUE;
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}
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}
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break;
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case MVE_VQSHL_T2:
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case MVE_VQSHLU_T3:
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case MVE_VRSHR:
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case MVE_VSHL_T1:
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case MVE_VSHR:
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case MVE_VSLI:
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case MVE_VSRI:
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{
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unsigned long sz = arm_decode_field (given, 19, 21);
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if ((sz & 7) == 1)
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return FALSE;
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else if ((sz & 6) == 2)
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return FALSE;
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else if ((sz & 4) == 4)
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return FALSE;
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else
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{
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*undefined_code = UNDEF_SIZE;
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return TRUE;
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}
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}
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case MVE_VQRSHRN:
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case MVE_VQRSHRUN:
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if (arm_decode_field (given, 19, 20) == 0)
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{
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*undefined_code = UNDEF_SIZE_0;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -5309,6 +5580,11 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VQRSHL_T2:
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case MVE_VQSHL_T1:
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case MVE_VRSHL_T2:
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case MVE_VSHL_T2:
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case MVE_VSHLC:
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case MVE_VQDMLAH:
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case MVE_VQRDMLAH:
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case MVE_VQDMLASH:
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@ -5897,6 +6173,10 @@ print_mve_undefined (struct disassemble_info *info,
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switch (undefined_code)
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{
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case UNDEF_SIZE:
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func (stream, "illegal size");
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break;
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case UNDEF_SIZE_0:
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func (stream, "size equals zero");
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break;
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@ -6403,8 +6683,17 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VQRDMULH_T2:
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case MVE_VQDMULH_T3:
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case MVE_VQRDMULH_T4:
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case MVE_VQRSHL_T1:
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case MVE_VQRSHL_T2:
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case MVE_VQSHL_T1:
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case MVE_VQSHL_T4:
|
||||
case MVE_VRHADD:
|
||||
case MVE_VRINT_FP:
|
||||
case MVE_VRSHL_T1:
|
||||
case MVE_VRSHL_T2:
|
||||
case MVE_VSHL_T2:
|
||||
case MVE_VSHL_T3:
|
||||
case MVE_VSHLL_T2:
|
||||
case MVE_VST2:
|
||||
case MVE_VST4:
|
||||
case MVE_VSTRB_SCATTER_T1:
|
||||
|
|
@ -6563,11 +6852,95 @@ print_mve_size (struct disassemble_info *info,
|
|||
}
|
||||
break;
|
||||
|
||||
case MVE_VQSHRN:
|
||||
case MVE_VQSHRUN:
|
||||
case MVE_VQRSHRN:
|
||||
case MVE_VQRSHRUN:
|
||||
case MVE_VRSHRN:
|
||||
case MVE_VSHRN:
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
case 2: case 3:
|
||||
func (stream, "32");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case MVE_VQSHL_T2:
|
||||
case MVE_VQSHLU_T3:
|
||||
case MVE_VRSHR:
|
||||
case MVE_VSHL_T1:
|
||||
case MVE_VSHLL_T1:
|
||||
case MVE_VSHR:
|
||||
case MVE_VSLI:
|
||||
case MVE_VSRI:
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
func (stream, "8");
|
||||
break;
|
||||
|
||||
case 2: case 3:
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
case 4: case 5: case 6: case 7:
|
||||
func (stream, "32");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
print_mve_shift_n (struct disassemble_info *info, long given,
|
||||
enum mve_instructions matched_insn)
|
||||
{
|
||||
void *stream = info->stream;
|
||||
fprintf_ftype func = info->fprintf_func;
|
||||
|
||||
int startAt0
|
||||
= matched_insn == MVE_VQSHL_T2
|
||||
|| matched_insn == MVE_VQSHLU_T3
|
||||
|| matched_insn == MVE_VSHL_T1
|
||||
|| matched_insn == MVE_VSHLL_T1
|
||||
|| matched_insn == MVE_VSLI;
|
||||
|
||||
unsigned imm6 = (given & 0x3f0000) >> 16;
|
||||
|
||||
if (matched_insn == MVE_VSHLL_T1)
|
||||
imm6 &= 0x1f;
|
||||
|
||||
unsigned shiftAmount = 0;
|
||||
if ((imm6 & 0x20) != 0)
|
||||
shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
|
||||
else if ((imm6 & 0x10) != 0)
|
||||
shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
|
||||
else if ((imm6 & 0x08) != 0)
|
||||
shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
|
||||
else
|
||||
print_mve_undefined (info, UNDEF_SIZE_0);
|
||||
|
||||
func (stream, "%u", shiftAmount);
|
||||
}
|
||||
|
||||
static void
|
||||
print_vec_condition (struct disassemble_info *info, long given,
|
||||
enum mve_instructions matched_insn)
|
||||
|
|
@ -8207,8 +8580,42 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
case 'd':
|
||||
func (stream, "%ld", value);
|
||||
value_in_comment = value;
|
||||
if (insn->mve_op == MVE_VQSHL_T2
|
||||
|| insn->mve_op == MVE_VQSHLU_T3
|
||||
|| insn->mve_op == MVE_VRSHR
|
||||
|| insn->mve_op == MVE_VRSHRN
|
||||
|| insn->mve_op == MVE_VSHL_T1
|
||||
|| insn->mve_op == MVE_VSHLL_T1
|
||||
|| insn->mve_op == MVE_VSHR
|
||||
|| insn->mve_op == MVE_VSHRN
|
||||
|| insn->mve_op == MVE_VSLI
|
||||
|| insn->mve_op == MVE_VSRI)
|
||||
print_mve_shift_n (info, given, insn->mve_op);
|
||||
else if (insn->mve_op == MVE_VSHLL_T2)
|
||||
{
|
||||
switch (value)
|
||||
{
|
||||
case 0x00:
|
||||
func (stream, "8");
|
||||
break;
|
||||
case 0x01:
|
||||
func (stream, "16");
|
||||
break;
|
||||
case 0x10:
|
||||
print_mve_undefined (info, UNDEF_SIZE_0);
|
||||
break;
|
||||
default:
|
||||
assert (0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (insn->mve_op == MVE_VSHLC && value == 0)
|
||||
value = 32;
|
||||
func (stream, "%ld", value);
|
||||
value_in_comment = value;
|
||||
}
|
||||
break;
|
||||
case 'F':
|
||||
func (stream, "s%ld", value);
|
||||
|
|
|
|||
Loading…
Reference in New Issue