[PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (print_insn_thumb32): Handle new instructions.
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@ -1,3 +1,9 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (thumb32_opcodes): Add new instructions.
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(print_insn_thumb32): Handle new instructions.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -3949,13 +3949,21 @@ static const struct opcode32 thumb32_opcodes[] =
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/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
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instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
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0xf00fe001, 0xffffffff, "lctp%c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf02fc001, 0xfffff001, "le\t%P"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf00fc001, 0xfffff001, "le\tlr, %P"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf01fc001, 0xfffff001, "letp\tlr, %P"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
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@ -10171,6 +10179,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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switch (*c)
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{
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case 's':
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if (val <= 3)
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func (stream, "%s", mve_vec_sizename[val]);
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else
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func (stream, "<undef size>");
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break;
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case 'd':
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func (stream, "%lu", val);
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value_in_comment = val;
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