MIPS: Fix encoding for MIPSr6 sigrie instruction.
The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
This commit is contained in:
parent
830db0485e
commit
d2159fdc0f
|
@ -1,3 +1,9 @@
|
||||||
|
2018-02-12 Henry Wong <henry@stuffedcow.net>
|
||||||
|
|
||||||
|
* testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix.
|
||||||
|
* testsuite/gas/mips/r6-n32.d: Likewise.
|
||||||
|
* testsuite/gas/mips/r6-n64.d: Likewise.
|
||||||
|
|
||||||
2018-02-12 Nick Clifton <nickc@redhat.com>
|
2018-02-12 Nick Clifton <nickc@redhat.com>
|
||||||
|
|
||||||
* po/ru.po: Updated Russian translation.
|
* po/ru.po: Updated Russian translation.
|
||||||
|
|
|
@ -497,6 +497,6 @@ Disassembly of section .text:
|
||||||
0+0598 <[^>]*> 41600024 dvp
|
0+0598 <[^>]*> 41600024 dvp
|
||||||
0+059c <[^>]*> 41620004 evp v0
|
0+059c <[^>]*> 41620004 evp v0
|
||||||
0+05a0 <[^>]*> 41620024 dvp v0
|
0+05a0 <[^>]*> 41620024 dvp v0
|
||||||
0+05a4 <[^>]*> 41700000 sigrie 0x0
|
0+05a4 <[^>]*> 04170000 sigrie 0x0
|
||||||
0+05a8 <[^>]*> 4170ffff sigrie 0xffff
|
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
|
||||||
\.\.\.
|
\.\.\.
|
||||||
|
|
|
@ -753,6 +753,6 @@ Disassembly of section .text:
|
||||||
0+0598 <[^>]*> 41600024 dvp
|
0+0598 <[^>]*> 41600024 dvp
|
||||||
0+059c <[^>]*> 41620004 evp v0
|
0+059c <[^>]*> 41620004 evp v0
|
||||||
0+05a0 <[^>]*> 41620024 dvp v0
|
0+05a0 <[^>]*> 41620024 dvp v0
|
||||||
0+05a4 <[^>]*> 41700000 sigrie 0x0
|
0+05a4 <[^>]*> 04170000 sigrie 0x0
|
||||||
0+05a8 <[^>]*> 4170ffff sigrie 0xffff
|
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
|
||||||
\.\.\.
|
\.\.\.
|
||||||
|
|
|
@ -496,6 +496,6 @@ Disassembly of section .text:
|
||||||
0+0598 <[^>]*> 41600024 dvp
|
0+0598 <[^>]*> 41600024 dvp
|
||||||
0+059c <[^>]*> 41620004 evp v0
|
0+059c <[^>]*> 41620004 evp v0
|
||||||
0+05a0 <[^>]*> 41620024 dvp v0
|
0+05a0 <[^>]*> 41620024 dvp v0
|
||||||
0+05a4 <[^>]*> 41700000 sigrie 0x0
|
0+05a4 <[^>]*> 04170000 sigrie 0x0
|
||||||
0+05a8 <[^>]*> 4170ffff sigrie 0xffff
|
0+05a8 <[^>]*> 0417ffff sigrie 0xffff
|
||||||
\.\.\.
|
\.\.\.
|
||||||
|
|
|
@ -1,3 +1,7 @@
|
||||||
|
2018-02-12 Henry Wong <henry@stuffedcow.net>
|
||||||
|
|
||||||
|
* mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
|
||||||
|
|
||||||
2018-02-05 Nick Clifton <nickc@redhat.com>
|
2018-02-05 Nick Clifton <nickc@redhat.com>
|
||||||
|
|
||||||
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
||||||
|
|
|
@ -1867,7 +1867,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||||
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
|
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
|
||||||
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
|
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
|
||||||
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
|
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
|
||||||
{"sigrie", "u", 0x41700000, 0xffff0000, TRAP, 0, I37, 0, 0 },
|
{"sigrie", "u", 0x04170000, 0xffff0000, TRAP, 0, I37, 0, 0 },
|
||||||
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 },
|
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 },
|
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
|
{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
|
||||||
|
|
Loading…
Reference in New Issue