[PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
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@ -1,3 +1,15 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_undefined): Add new reasons.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -152,6 +152,29 @@ enum mve_instructions
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MVE_VQDMULL_T2,
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MVE_VQMOVN,
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MVE_VQMOVUN,
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MVE_VADDV,
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MVE_VMLADAV_T1,
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MVE_VMLADAV_T2,
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MVE_VMLALDAV,
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MVE_VMLAS,
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MVE_VADDLV,
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MVE_VMLSDAV_T1,
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MVE_VMLSDAV_T2,
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MVE_VMLSLDAV,
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MVE_VRMLALDAVH,
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MVE_VRMLSLDAVH,
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MVE_VQDMLADH,
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MVE_VQRDMLADH,
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MVE_VQDMLAH,
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MVE_VQRDMLAH,
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MVE_VQDMLASH,
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MVE_VQRDMLASH,
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MVE_VQDMLSDH,
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MVE_VQRDMLSDH,
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MVE_VQDMULH_T1,
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MVE_VQRDMULH_T2,
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MVE_VQDMULH_T3,
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MVE_VQRDMULH_T4,
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MVE_NONE
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};
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@ -203,6 +226,7 @@ enum mve_undefined
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op2 == 0 and op1 == (0 or 1). */
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UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
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in {0xx1, x0x1}. */
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UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -1922,9 +1946,11 @@ static const struct opcode32 neon_opcodes[] =
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%E print vmov, vmvn, vorr, vbic encoded constant
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%N print generic index for vmov
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%T print bottom ('b') or top ('t') of source register
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%X print exchange field in vmla* instructions
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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%<bitfield>A print accumulate or not
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%<bitfield>Q print as a MVE Q register
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%<bitfield>F print as a MVE S register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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@ -1999,6 +2025,18 @@ static const struct mopcode32 mve_opcodes[] =
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0xef100150, 0xffb11f51,
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"vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VADDLV. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADDLV,
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0xee890f00, 0xef8f1fd1,
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"vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
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/* Vector VADDV. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADDV,
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0xeef10f00, 0xeff31fd1,
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"vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
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/* Vector VCMP floating point T1. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCMP_FP_T1,
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@ -2222,6 +2260,74 @@ static const struct mopcode32 mve_opcodes[] =
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0xec101f00, 0xfe101f80,
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"vldrw%v.u32\t%13-15,22Q, %d"},
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/* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
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opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLALDAV,
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0xee801e00, 0xef801f51,
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"vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLALDAV,
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0xee800e00, 0xef801f51,
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"vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLADAV_T1,
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0xeef00e00, 0xeff01f51,
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"vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLADAV_T2,
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0xeef00f00, 0xeff11f51,
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"vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMLADAV T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLADAV_T1,
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0xeef01e00, 0xeff01f51,
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"vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMLADAV T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLADAV_T2,
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0xeef01f00, 0xeff11f51,
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"vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMLAS. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLAS,
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0xee011e40, 0xef811f70,
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"vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
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opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRMLSLDAVH,
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0xfe800e01, 0xff810f51,
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"vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
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opcdoe aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLSLDAV,
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0xee800e01, 0xff800f51,
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"vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VMLSDAV T1 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLSDAV_T1,
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0xeef00e01, 0xfff00f51,
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"vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMLSDAV T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMLSDAV_T2,
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0xfef00e01, 0xfff10f51,
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"vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
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/* Vector VMOV between gpr and half precision register, op == 0. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOV_HFP_TO_GP,
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@ -2367,12 +2473,96 @@ static const struct mopcode32 mve_opcodes[] =
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0xee310e81, 0xffb30fd1,
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"vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VQDMLADH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMLADH,
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0xee000e00, 0xff810f51,
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"vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQRDMLADH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMLADH,
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0xee000e01, 0xff810f51,
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"vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQDMLAH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMLAH,
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0xee000e60, 0xef811f70,
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"vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQRDMLAH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMLAH,
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0xee000e40, 0xef811f70,
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"vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQDMLASH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMLASH,
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0xee001e60, 0xef811f70,
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"vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQRDMLASH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMLASH,
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0xee001e40, 0xef811f70,
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"vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQDMLSDH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMLSDH,
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0xfe000e00, 0xff810f51,
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"vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQRDMLSDH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMLSDH,
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0xfe000e01, 0xff810f51,
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"vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQDMULH T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMULH_T1,
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0xef000b40, 0xff811f51,
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"vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQRDMULH T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMULH_T2,
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0xff000b40, 0xff811f51,
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"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQDMULH T3 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMULH_T3,
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0xee010e60, 0xff811f70,
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"vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQRDMULH T4 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQRDMULH_T4,
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0xfe010e60, 0xff811f70,
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"vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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0xffb20440, 0xffb31c51,
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"vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VRMLALDAVH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRMLALDAVH,
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0xee800f00, 0xef811f51,
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"vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VRMLALDAVH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VRMLALDAVH,
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0xee801f00, 0xef811f51,
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"vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
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/* Vector VST2 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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@ -4477,6 +4667,17 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VQRDMLADH:
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case MVE_VQDMLAH:
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case MVE_VQRDMLAH:
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case MVE_VQDMLASH:
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case MVE_VQRDMLASH:
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case MVE_VQDMLSDH:
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case MVE_VQRDMLSDH:
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case MVE_VQDMULH_T3:
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case MVE_VQRDMULH_T4:
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case MVE_VQDMLADH:
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case MVE_VMLAS:
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case MVE_VMULL_INT:
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case MVE_VHADD_T2:
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case MVE_VHSUB_T2:
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@ -4569,6 +4770,7 @@ is_mve_encoding_conflict (unsigned long given,
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return FALSE;
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}
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case MVE_VADDV:
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case MVE_VMOVN:
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case MVE_VQMOVUN:
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case MVE_VQMOVN:
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@ -4577,6 +4779,21 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VMLSLDAV:
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case MVE_VRMLSLDAVH:
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case MVE_VMLALDAV:
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case MVE_VADDLV:
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if (arm_decode_field (given, 20, 22) == 7)
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return TRUE;
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else
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return FALSE;
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case MVE_VRMLALDAVH:
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if ((arm_decode_field (given, 20, 22) & 6) == 6)
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return TRUE;
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else
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return FALSE;
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default:
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return FALSE;
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@ -4678,6 +4895,8 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VQDMULH_T1:
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case MVE_VQRDMULH_T2:
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case MVE_VRHADD:
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case MVE_VHADD_T1:
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case MVE_VHSUB_T1:
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@ -4939,6 +5158,19 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VRMLALDAVH:
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case MVE_VMLADAV_T1:
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case MVE_VMLADAV_T2:
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case MVE_VMLALDAV:
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if ((arm_decode_field (given, 28, 28) == 1)
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&& (arm_decode_field (given, 12, 12) == 1))
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{
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*undefined_code = UNDEF_XCHG_UNS;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -4998,6 +5230,13 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VQDMLAH:
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case MVE_VQRDMLAH:
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case MVE_VQDMLASH:
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case MVE_VQRDMLASH:
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case MVE_VQDMULH_T3:
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case MVE_VQRDMULH_T4:
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case MVE_VMLAS:
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case MVE_VFMA_FP_SCALAR:
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case MVE_VFMAS_FP_SCALAR:
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case MVE_VHADD_T2:
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@ -5210,6 +5449,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VQRDMLADH:
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case MVE_VQDMLSDH:
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case MVE_VQRDMLSDH:
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case MVE_VQDMLADH:
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case MVE_VMULL_INT:
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{
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unsigned long Qd;
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@ -5290,6 +5533,18 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VMLSLDAV:
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case MVE_VRMLSLDAVH:
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case MVE_VMLALDAV:
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case MVE_VADDLV:
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if (arm_decode_field (given, 20, 22) == 6)
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -5556,6 +5811,10 @@ print_mve_undefined (struct disassemble_info *info,
|
||||
func (stream, "op field equal 0 and bad cmode");
|
||||
break;
|
||||
|
||||
case UNDEF_XCHG_UNS:
|
||||
func (stream, "exchange and unsigned together");
|
||||
break;
|
||||
|
||||
case UNDEF_NONE:
|
||||
break;
|
||||
}
|
||||
@ -5915,6 +6174,7 @@ print_mve_size (struct disassemble_info *info,
|
||||
|
||||
switch (matched_insn)
|
||||
{
|
||||
case MVE_VADDV:
|
||||
case MVE_VCMP_VEC_T1:
|
||||
case MVE_VCMP_VEC_T2:
|
||||
case MVE_VCMP_VEC_T3:
|
||||
@ -5933,12 +6193,25 @@ print_mve_size (struct disassemble_info *info,
|
||||
case MVE_VLDRD_GATHER_T4:
|
||||
case MVE_VLDRB_T1:
|
||||
case MVE_VLDRH_T2:
|
||||
case MVE_VMLAS:
|
||||
case MVE_VPT_VEC_T1:
|
||||
case MVE_VPT_VEC_T2:
|
||||
case MVE_VPT_VEC_T3:
|
||||
case MVE_VPT_VEC_T4:
|
||||
case MVE_VPT_VEC_T5:
|
||||
case MVE_VPT_VEC_T6:
|
||||
case MVE_VQDMLADH:
|
||||
case MVE_VQRDMLADH:
|
||||
case MVE_VQDMLAH:
|
||||
case MVE_VQRDMLAH:
|
||||
case MVE_VQDMLASH:
|
||||
case MVE_VQRDMLASH:
|
||||
case MVE_VQDMLSDH:
|
||||
case MVE_VQRDMLSDH:
|
||||
case MVE_VQDMULH_T1:
|
||||
case MVE_VQRDMULH_T2:
|
||||
case MVE_VQDMULH_T3:
|
||||
case MVE_VQRDMULH_T4:
|
||||
case MVE_VRHADD:
|
||||
case MVE_VRINT_FP:
|
||||
case MVE_VST2:
|
||||
@ -5968,6 +6241,10 @@ print_mve_size (struct disassemble_info *info,
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
case MVE_VMLADAV_T1:
|
||||
case MVE_VMLALDAV:
|
||||
case MVE_VMLSDAV_T1:
|
||||
case MVE_VMLSLDAV:
|
||||
case MVE_VMOVN:
|
||||
case MVE_VQDMULL_T1:
|
||||
case MVE_VQDMULL_T2:
|
||||
@ -7639,6 +7916,11 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
func (stream, "t");
|
||||
break;
|
||||
|
||||
case 'X':
|
||||
if (arm_decode_field (given, 12, 12) == 1)
|
||||
func (stream, "x");
|
||||
break;
|
||||
|
||||
case '0': case '1': case '2': case '3': case '4':
|
||||
case '5': case '6': case '7': case '8': case '9':
|
||||
{
|
||||
@ -7662,6 +7944,10 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
value,
|
||||
insn->mve_op);
|
||||
break;
|
||||
case 'A':
|
||||
if (value == 1)
|
||||
func (stream, "a");
|
||||
break;
|
||||
case 'i':
|
||||
{
|
||||
unsigned long imm
|
||||
|
Loading…
Reference in New Issue
Block a user