* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
argument. * mips-opc.c (G6): Undefine. (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro as the first "move" alternative.
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@ -1,3 +1,11 @@
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2001-08-10 Richard Sandiford <rsandifo@redhat.com>
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* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
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argument.
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* mips-opc.c (G6): Undefine.
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(mips_builtin_opcodes): Remove gp32 entry for "move". Add macro
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as the first "move" alternative.
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2001-08-10 Andreas Jaeger <aj@suse.de>
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2001-08-10 Andreas Jaeger <aj@suse.de>
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* configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes
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* configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes
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@ -469,7 +469,7 @@ print_insn_mips (memaddr, word, info)
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{
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{
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register const char *d;
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register const char *d;
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if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
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if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
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continue;
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continue;
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(*info->fprintf_func) (info->stream, "%s", op->name);
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(*info->fprintf_func) (info->stream, "%s", op->name);
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@ -96,8 +96,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define G3 (I4 \
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#define G3 (I4 \
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)
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)
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#define G6 INSN_GP32
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/* The order of overloaded instructions matters. Label arguments and
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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register arguments look the same. Instructions that can have either
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for arguments must apear in the correct order in this table for the
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for arguments must apear in the correct order in this table for the
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@ -121,7 +119,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
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{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
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{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
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{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
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{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
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{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
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{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */
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{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
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{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
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{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
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{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
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{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
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{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
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{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
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