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opcodes: discriminate endianness and insn-endianness in CGEN ports 

The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value.  These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.

The process of writing an instruction to the object file is:

  a) cgen_put_insn_value        ;; Writes out the opcodes.
  b) ARCH_cgen_insert_operand
       insert_normal
         insert_1
           cgen_put_insn_value  ;; Writes out the bytes of the
                                ;; operand.

Likewise, the process of reading an instruction from the object file
is:

  a) cgen_get_insn_value        ;; Reads the opcodes.
  b) ARCH_cgen_extract_operand
       extract_normal
         extract_1
           cgen_get_insn_value  ;; Reads in the bytes of the
                                ;; operand.

As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.

This is problematic for architectures in which the endianness of
instructions is different to the endianness of data.  An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.

This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate.  Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.

A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value.  It has been adapted to
  pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
  It has been adapted to pass the new endianargument.  Ditto for a
  call in the assembler.

Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/cgen.h: Get an `endian' argument in both
	cgen_get_insn_value and cgen_put_insn_value.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen.c (gas_cgen_finish_insn): Pass the endianness to
	cgen_put_insn_value.
	(gas_cgen_md_apply_fix): Likewise.
	(gas_cgen_md_apply_fix): Likewise.
	* config/tc-bpf.c (md_apply_fix): Pass data endianness to
	cgen_put_insn_value.
	* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
	cgen_put_insn_value.

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* mep.opc (print_slot_insn): Pass the insn endianness to
	cgen_get_insn_value.
This commit is contained in:
Jose E. Marchesi 2020-06-04 16:15:53 +02:00
parent b3db6d07be
commit e9bffec9af
40 changed files with 178 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
cpu/ChangeLog
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@ -1,3 +1,8 @@
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to
cgen_get_insn_value.
2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
David Faust <david.faust@oracle.com>

2
cpu/mep.opc
View File

@ -1271,7 +1271,7 @@ print_slot_insn (CGEN_CPU_DESC cd,
CGEN_INSN_INT insn_value;
CGEN_EXTRACT_INFO ex_info;
insn_value = cgen_get_insn_value (cd, buf, 32);
insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call
read_insn, since the incoming buffer is already read (and possibly

11
gas/ChangeLog
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@ -1,3 +1,14 @@
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to
cgen_put_insn_value.
(gas_cgen_md_apply_fix): Likewise.
(gas_cgen_md_apply_fix): Likewise.
* config/tc-bpf.c (md_apply_fix): Pass data endianness to
cgen_put_insn_value.
* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
cgen_put_insn_value.
2020-06-04 Alan Modra <amodra@gmail.com>
* testsuite/config/default.exp: Remove global directive outside

9
gas/cgen.c
View File

@ -621,7 +621,8 @@ gas_cgen_finish_insn (const CGEN_INSN *insn, CGEN_INSN_BYTES_PTR buf,
/* If we're recording insns as numbers (rather than a string of bytes),
target byte order handling is deferred until now. */
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf);
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf,
gas_cgen_cpu_desc->insn_endian);
#else
memcpy (f, buf, byte_len);
#endif
@ -906,13 +907,15 @@ gas_cgen_md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
CGEN_INSN_INT insn_value =
cgen_get_insn_value (cd, (unsigned char *) where,
CGEN_INSN_BITSIZE (insn));
CGEN_INSN_BITSIZE (insn),
cd->insn_endian);
/* ??? 0 is passed for `pc'. */
errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields,
&insn_value, (bfd_vma) 0);
cgen_put_insn_value (cd, (unsigned char *) where,
CGEN_INSN_BITSIZE (insn), insn_value);
CGEN_INSN_BITSIZE (insn), insn_value,
cd->insn_endian);
}
#else
/* ??? 0 is passed for `pc'. */

3
gas/config/tc-bpf.c
View File

@ -324,7 +324,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg)
this code is executed only once per instruction. */
where = fixP->fx_frag->fr_literal + fixP->fx_where;
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) where + 1, 8,
target_big_endian ? 0x01 : 0x10);
target_big_endian ? 0x01 : 0x10,
gas_cgen_cpu_desc->endian);
/* Fallthrough. */
case BPF_OPERAND_DISP16:
/* The PC-relative displacement fields in jump instructions

2
gas/config/tc-mep.c
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@ -1111,7 +1111,7 @@ mep_check_ivc2_scheduling (void)
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
m->buffer[0]);
m->buffer[0], gas_cgen_cpu_desc->insn_endian);
#else
memcpy (temp, m->buffer, byte_len);
#endif

5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/cgen.h: Get an `endian' argument in both
cgen_get_insn_value and cgen_put_insn_value.
2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
* opcode/cgen.h (enum cgen_cpu_open_arg): New value

4
include/opcode/cgen.h
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@ -1463,9 +1463,9 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands
/* Cover fns to bfd_get/set. */
extern CGEN_INSN_INT cgen_get_insn_value
(CGEN_CPU_DESC, unsigned char *, int);
(CGEN_CPU_DESC, unsigned char *, int, int);
extern void cgen_put_insn_value
(CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
(CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int);
extern CGEN_INSN_INT cgen_get_base_insn_value
(CGEN_CPU_DESC, unsigned char *, int);

43
opcodes/ChangeLog
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@ -1,3 +1,46 @@
2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
(cgen_put_insn_value): Likewise.
(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
* cgen-dis.in (print_insn): Likewise.
* cgen-ibld.in (insert_1): Likewise.
(insert_1): Likewise.
(insert_insn_normal): Likewise.
(extract_1): Likewise.
* bpf-dis.c: Regenerate.
* bpf-ibld.c: Likewise.
* bpf-ibld.c: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* epiphany-dis.c: Likewise.
* epiphany-ibld.c: Likewise.
* fr30-dis.c: Likewise.
* fr30-ibld.c: Likewise.
* frv-dis.c: Likewise.
* frv-ibld.c: Likewise.
* ip2k-dis.c: Likewise.
* ip2k-ibld.c: Likewise.
* iq2000-dis.c: Likewise.
* iq2000-ibld.c: Likewise.
* lm32-dis.c: Likewise.
* lm32-ibld.c: Likewise.
* m32c-dis.c: Likewise.
* m32c-ibld.c: Likewise.
* m32r-dis.c: Likewise.
* m32r-ibld.c: Likewise.
* mep-dis.c: Likewise.
* mep-ibld.c: Likewise.
* mt-dis.c: Likewise.
* mt-ibld.c: Likewise.
* or1k-dis.c: Likewise.
* or1k-ibld.c: Likewise.
* xc16x-dis.c: Likewise.
* xc16x-ibld.c: Likewise.
* xstormy16-dis.c: Likewise.
* xstormy16-ibld.c: Likewise.
2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
* cgen-dis.in (cpu_desc_list): New field `insn_endian'.

2
opcodes/bpf-dis.c
View File

@ -376,7 +376,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/bpf-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/cgen-dis.in
View File

@ -210,7 +210,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/cgen-ibld.in
View File

@ -87,7 +87,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -97,7 +97,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -268,8 +268,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -386,7 +386,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

18
opcodes/cgen-opc.c
View File

@ -357,9 +357,10 @@ cgen_macro_insn_count (CGEN_CPU_DESC cd)
/* Cover function to read and properly byteswap an insn value. */
CGEN_INSN_INT
cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length,
int endian)
{
int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
int big_p = (endian == CGEN_ENDIAN_BIG);
int insn_chunk_bitsize = cd->insn_chunk_bitsize;
CGEN_INSN_INT value = 0;
@ -385,7 +386,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
}
else
{
value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG);
value = bfd_get_bits (buf, length, endian == CGEN_ENDIAN_BIG);
}
return value;
@ -397,9 +398,10 @@ void
cgen_put_insn_value (CGEN_CPU_DESC cd,
unsigned char *buf,
int length,
CGEN_INSN_INT value)
CGEN_INSN_INT value,
int endian)
{
int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG);
int big_p = (endian == CGEN_ENDIAN_BIG);
int insn_chunk_bitsize = cd->insn_chunk_bitsize;
if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length)
@ -459,7 +461,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd,
{
info = NULL;
insn_bytes_value = (unsigned char *) xmalloc (cd->max_insn_bitsize / 8);
cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value);
cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value,
cd->insn_endian);
}
else
{
@ -467,7 +470,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd,
ex_info.dis_info = NULL;
ex_info.insn_bytes = insn_bytes_value;
ex_info.valid = -1;
insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length);
insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length,
cd->insn_endian);
}
if (!insn)

2
opcodes/epiphany-dis.c
View File

@ -451,7 +451,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/epiphany-ibld.c
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@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/fr30-dis.c
View File

@ -472,7 +472,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/fr30-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/frv-dis.c
View File

@ -569,7 +569,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/frv-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/ip2k-dis.c
View File

@ -461,7 +461,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/ip2k-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/iq2000-dis.c
View File

@ -362,7 +362,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/iq2000-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/lm32-dis.c
View File

@ -320,7 +320,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/lm32-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/m32c-dis.c
View File

@ -1064,7 +1064,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/m32c-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/m32r-dis.c
View File

@ -452,7 +452,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/m32r-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

4
opcodes/mep-dis.c
View File

@ -467,7 +467,7 @@ print_slot_insn (CGEN_CPU_DESC cd,
CGEN_INSN_INT insn_value;
CGEN_EXTRACT_INFO ex_info;
insn_value = cgen_get_insn_value (cd, buf, 32);
insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call
read_insn, since the incoming buffer is already read (and possibly
@ -1360,7 +1360,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/mep-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/mt-dis.c
View File

@ -463,7 +463,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/mt-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/or1k-dis.c
View File

@ -347,7 +347,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/or1k-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/xc16x-dis.c
View File

@ -593,7 +593,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/xc16x-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;

2
opcodes/xstormy16-dis.c
View File

@ -341,7 +341,7 @@ print_insn (CGEN_CPU_DESC cd,
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize);
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call

10
opcodes/xstormy16-ibld.c
View File

@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd,
unsigned long x,mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd,
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value);
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd,
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length);
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;