* xtensa-tdep.h (xtensa_reg_mask_t): New.
(xtensa_mask_t): Change mask field to be a separate array. * xtensa-tdep.c (extract_call_winsize, xtensa_pseudo_register_read) (xtensa_pseudo_register_write, xtensa_unwind_pc) (xtensa_unwind_dummy_id, xtensa_push_dummy_call) (xtensa_breakpoint_from_pc): Remove implicit type casting. * xtensa-config.c (mask0, mask1, mask2, mask3, mask4, mask5) (mask6, mask7, mask8, mask9, mask10, mask11, mask12, mask13) (mask14, mask15): Rename to (xtensa_mask0, xtensa_mask1, xtensa_mask2, xtensa_mask3) (xtensa_mask4, xtensa_mask5, xtensa_mask6, xtensa_mask7) (xtensa_mask8, xtensa_mask9, xtensa_mask10, xtensa_mask11) (xtensa_mask12, xtensa_mask13, xtensa_mask14, xtensa_mask15): this. (xtensa_submask0, xtensa_submask1, xtensa_submask2, xtensa_submask3) (xtensa_submask4, xtensa_submask5, xtensa_submask6, xtensa_submask7) (xtensa_submask8, xtensa_submask9, xtensa_submask10) (xtensa_submask11, xtensa_submask12, xtensa_submask13) (xtensa_submask14, xtensa_submask15): New. (rmap): Follow strict aliasing rules doing static initialization.
This commit is contained in:
Maxim Grigoriev
parent
a8e24a5610
commit
ff7a4c00e0
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@ -1,3 +1,25 @@
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2007-02-15 Maxim Grigoriev <maxim2405@gmail.com>
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* xtensa-tdep.h (xtensa_reg_mask_t): New.
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(xtensa_mask_t): Change mask field to be a separate array.
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* xtensa-tdep.c (extract_call_winsize, xtensa_pseudo_register_read)
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(xtensa_pseudo_register_write, xtensa_unwind_pc)
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(xtensa_unwind_dummy_id, xtensa_push_dummy_call)
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(xtensa_breakpoint_from_pc): Remove implicit type casting.
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* xtensa-config.c (mask0, mask1, mask2, mask3, mask4, mask5)
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(mask6, mask7, mask8, mask9, mask10, mask11, mask12, mask13)
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(mask14, mask15): Rename to
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(xtensa_mask0, xtensa_mask1, xtensa_mask2, xtensa_mask3)
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(xtensa_mask4, xtensa_mask5, xtensa_mask6, xtensa_mask7)
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(xtensa_mask8, xtensa_mask9, xtensa_mask10, xtensa_mask11)
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(xtensa_mask12, xtensa_mask13, xtensa_mask14, xtensa_mask15): this.
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(xtensa_submask0, xtensa_submask1, xtensa_submask2, xtensa_submask3)
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(xtensa_submask4, xtensa_submask5, xtensa_submask6, xtensa_submask7)
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(xtensa_submask8, xtensa_submask9, xtensa_submask10)
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(xtensa_submask11, xtensa_submask12, xtensa_submask13)
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(xtensa_submask14, xtensa_submask15): New.
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(rmap): Follow strict aliasing rules doing static initialization.
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2007-02-13 Daniel Jacobowitz <dan@codesourcery.com>
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* target-descriptions.c (tdesc_named_type): Move code_ptr and data_ptr
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@ -56,22 +56,38 @@ xtensa_config_tdep (struct gdbarch_info *info)
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/* Masked registers. */
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const int mask0[] = { 1, 96, 0, 4 };
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const int mask1[] = { 1, 96, 5, 1 };
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const int mask2[] = { 1, 96, 18, 1 };
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const int mask3[] = { 1, 96, 6, 2 };
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const int mask4[] = { 1, 96, 4, 1 };
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const int mask5[] = { 1, 96, 16, 2 };
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const int mask6[] = { 1, 96, 8, 4 };
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const int mask7[] = { 1, 95, 12, 20 };
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const int mask8[] = { 1, 95, 0, 1 };
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const int mask9[] = { 1, 108, 8, 4 };
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const int mask10[] = { 1, 109, 24, 8 };
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const int mask11[] = { 1, 109, 16, 8 };
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const int mask12[] = { 1, 109, 8, 8 };
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const int mask13[] = { 1, 110, 16, 2 };
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const int mask14[] = { 1, 111, 16, 2 };
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const int mask15[] = { 1, 67, 22, 10 };
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xtensa_reg_mask_t xtensa_submask0[] = { { 96, 0, 4 } };
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const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
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xtensa_reg_mask_t xtensa_submask1[] = { { 96, 5, 1 } };
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const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
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xtensa_reg_mask_t xtensa_submask2[] = { { 96, 18, 1 } };
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const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
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xtensa_reg_mask_t xtensa_submask3[] = { { 96, 6, 2 } };
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const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
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xtensa_reg_mask_t xtensa_submask4[] = { { 96, 4, 1 } };
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const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
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xtensa_reg_mask_t xtensa_submask5[] = { { 96, 16, 2 } };
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const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
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xtensa_reg_mask_t xtensa_submask6[] = { { 96, 8, 4 } };
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const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
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xtensa_reg_mask_t xtensa_submask7[] = { { 95, 12, 20 } };
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const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
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xtensa_reg_mask_t xtensa_submask8[] = { { 95, 0, 1 } };
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const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
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xtensa_reg_mask_t xtensa_submask9[] = { { 108, 8, 4 } };
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const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
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xtensa_reg_mask_t xtensa_submask10[] = { { 109, 24, 8 } };
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const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
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xtensa_reg_mask_t xtensa_submask11[] = { { 109, 16, 8 } };
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const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
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xtensa_reg_mask_t xtensa_submask12[] = { { 109, 8, 8 } };
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const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
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xtensa_reg_mask_t xtensa_submask13[] = { { 110, 16, 2 } };
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const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
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xtensa_reg_mask_t xtensa_submask14[] = { { 111, 16, 2 } };
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const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
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xtensa_reg_mask_t xtensa_submask15[] = { { 67, 22, 10 } };
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const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
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/* Register map. */
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@ -468,52 +484,52 @@ xtensa_register_t rmap[] =
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32, 4, 4, 0x0000000f, 0x0006, 0,
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0, 0 },
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{ /* 0130 */ "psintlevel", 520, xtRegisterTypeMapped, 0x1010, 0,
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4, 4, 4, 0x00002004, 0x0006, (xtensa_mask_t *) mask0,
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4, 4, 4, 0x00002004, 0x0006, &xtensa_mask0,
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0, 0 },
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{ /* 0131 */ "psum", 524, xtRegisterTypeMapped, 0x1010, 0,
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1, 4, 4, 0x00002005, 0x0006, (xtensa_mask_t *) mask1,
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1, 4, 4, 0x00002005, 0x0006, &xtensa_mask1,
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0, 0 },
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{ /* 0132 */ "pswoe", 528, xtRegisterTypeMapped, 0x1010, 0,
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1, 4, 4, 0x00002006, 0x0006, (xtensa_mask_t *) mask2,
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1, 4, 4, 0x00002006, 0x0006, &xtensa_mask2,
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0, 0 },
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{ /* 0133 */ "psring", 532, xtRegisterTypeMapped, 0x1010, 0,
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2, 4, 4, 0x00002007, 0x0006, (xtensa_mask_t *) mask3,
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2, 4, 4, 0x00002007, 0x0006, &xtensa_mask3,
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0, 0 },
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{ /* 0134 */ "psexcm", 536, xtRegisterTypeMapped, 0x1010, 0,
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1, 4, 4, 0x00002008, 0x0006, (xtensa_mask_t *) mask4,
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1, 4, 4, 0x00002008, 0x0006, &xtensa_mask4,
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0, 0 },
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{ /* 0135 */ "pscallinc", 540, xtRegisterTypeMapped, 0x1010, 0,
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2, 4, 4, 0x00002009, 0x0006, (xtensa_mask_t *) mask5,
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2, 4, 4, 0x00002009, 0x0006, &xtensa_mask5,
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0, 0 },
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{ /* 0136 */ "psowb", 544, xtRegisterTypeMapped, 0x1010, 0,
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4, 4, 4, 0x0000200a, 0x0006, (xtensa_mask_t *) mask6,
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4, 4, 4, 0x0000200a, 0x0006, &xtensa_mask6,
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0, 0 },
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{ /* 0137 */ "litbaddr", 548, xtRegisterTypeMapped, 0x1010, 0,
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20, 4, 4, 0x0000200b, 0x0006, (xtensa_mask_t *) mask7,
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20, 4, 4, 0x0000200b, 0x0006, &xtensa_mask7,
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0, 0 },
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{ /* 0138 */ "litben", 552, xtRegisterTypeMapped, 0x1010, 0,
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1, 4, 4, 0x0000200c, 0x0006, (xtensa_mask_t *) mask8,
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1, 4, 4, 0x0000200c, 0x0006, &xtensa_mask8,
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0, 0 },
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{ /* 0139 */ "dbnum", 556, xtRegisterTypeMapped, 0x1010, 0,
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4, 4, 4, 0x00002011, 0x0006, (xtensa_mask_t *) mask9,
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4, 4, 4, 0x00002011, 0x0006, &xtensa_mask9,
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0, 0 },
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{ /* 0140 */ "asid3", 560, xtRegisterTypeMapped, 0x1010, 0,
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8, 4, 4, 0x00002012, 0x0006, (xtensa_mask_t *) mask10,
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8, 4, 4, 0x00002012, 0x0006, &xtensa_mask10,
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0, 0 },
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{ /* 0141 */ "asid2", 564, xtRegisterTypeMapped, 0x1010, 0,
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8, 4, 4, 0x00002013, 0x0006, (xtensa_mask_t *) mask11,
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8, 4, 4, 0x00002013, 0x0006, &xtensa_mask11,
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0, 0 },
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{ /* 0142 */ "asid1", 568, xtRegisterTypeMapped, 0x1010, 0,
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8, 4, 4, 0x00002014, 0x0006, (xtensa_mask_t *) mask12,
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8, 4, 4, 0x00002014, 0x0006, &xtensa_mask12,
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0, 0 },
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{ /* 0143 */ "instpgszid4", 572, xtRegisterTypeMapped, 0x1010, 0,
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2, 4, 4, 0x00002015, 0x0006, (xtensa_mask_t *) mask13,
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2, 4, 4, 0x00002015, 0x0006, &xtensa_mask13,
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0, 0 },
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{ /* 0144 */ "datapgszid4", 576, xtRegisterTypeMapped, 0x1010, 0,
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2, 4, 4, 0x00002016, 0x0006, (xtensa_mask_t *) mask14,
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2, 4, 4, 0x00002016, 0x0006, &xtensa_mask14,
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0, 0 },
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{ /* 0145 */ "ptbase", 580, xtRegisterTypeMapped, 0x1010, 0,
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10, 4, 4, 0x00002017, 0x0006, (xtensa_mask_t *) mask15,
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10, 4, 4, 0x00002017, 0x0006, &xtensa_mask15,
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0, 0 },
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};
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@ -140,7 +140,7 @@ extract_call_winsize (CORE_ADDR pc)
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{
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int winsize = 4; /* Default: No call, e.g. dummy frame. */
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int insn;
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char buf[4];
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gdb_byte buf[4];
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DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
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/* Read aliases a0..a15. */
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if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
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{
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char *buf = (char *) alloca (MAX_REGISTER_SIZE);
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gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
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regcache_raw_read (regcache, WB_REGNUM, buf);
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regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
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/* Renumber register, if aliase a0..a15. */
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if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
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{
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char *buf = (char *) alloca (MAX_REGISTER_SIZE);
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gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
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unsigned int wb;
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regcache_raw_read (regcache, WB_REGNUM, buf);
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@ -842,7 +842,7 @@ xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
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static CORE_ADDR
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xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
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{
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char buf[8];
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gdb_byte buf[8];
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DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
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@ -859,7 +859,7 @@ static struct frame_id
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xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
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{
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CORE_ADDR pc, fp;
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char buf[4];
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gdb_byte buf[4];
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/* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
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@ -1265,7 +1265,7 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch,
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{
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int i;
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int size, onstack_size;
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char *buf = (char *) alloca (16);
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gdb_byte *buf = (gdb_byte *) alloca (16);
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CORE_ADDR ra, ps;
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struct argument_info
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{
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@ -1493,10 +1493,10 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch,
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const unsigned char *
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xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
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{
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static char big_breakpoint[] = BIG_BREAKPOINT;
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static char little_breakpoint[] = LITTLE_BREAKPOINT;
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static char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
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static char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
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static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
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static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
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static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
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static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
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DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
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@ -101,15 +101,17 @@ typedef struct
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/* Mask. */
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typedef struct
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{
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int reg_num;
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int bit_start;
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int bit_size;
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} xtensa_reg_mask_t;
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typedef struct
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{
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int count;
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struct
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{
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int reg_num;
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int bit_start;
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int bit_size;
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} mask[0];
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xtensa_reg_mask_t *mask;
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} xtensa_mask_t;
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