architecture type. Add support for bfd_mach_v850e2 and
bfd_mach_v850e2v3 machine numbers.
* v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
(cmpf.d): Correct order of operands.
(cmpf.s): Likewise.
(trncf.dul): New pattern.
(trncf.duw): New pattern.
(trncf.sul): New pattern.
(trncf.suw): New pattern.
* v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
When the sim is built w/out the bfroms, we end up passing a length of 0 when
mapping the rom region which the core sim code rejects. So add an alias field
equal to the length to avoid that error.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The latest gdb sim-remote.c really wants a return value from the fetch/store
register functions, so update the Blackfin sim to avoid the warnings/errors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The change of include file introduces some new warnings about functions
being used without a prototype. So a few more system includes have been
added to compensate for that.
sim/d10v/ChangeLog:
* interp.c: #include "config.h" instead of "sysdep.h".
Add conditional include of string.h or strings.h, as well as
conditional include of stdlib.h.
This file includes "gdb/callback.h", which includes "bfd.h", which
itself verifies that "config.h" was included earlier.
sim/erc32/ChangeLog:
* sys.h: Include "config.h".
* wrapper.c: Include config.h before system header files.
* callback.c: Include config.h before system header files.
* cgen-trace.c: Likewise.
* cgen-utils.c: Likewise.
* gentmap.c: Likewise.
* sim-if.c: Include config.h before system header files.
* compile.c: Include config.h before system header files.
* sim-main.h: Likewise.
* gdb-if.c: Include config.h before system header files.
* load.c: Likewise.
* syscalls.c: Likewise.
* trace.c: Likewise.
* interp.c: Include config.h before system header files.
Newer BF54x parts feature an updated GPIO block where all the interrupt
handling is split off, so create a new model for the pin interrupts.
This is missing the port forwarding aspects, but at least the register
interface should be there.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
These are randomly generated tests to track down issues in ASTAT
handling with shift insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
More ASTAT directed fixes, but this time at the dsp32shift insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This improves some of the arithmetic shifts to better match the
hardware (especially wrt ASTAT behavior). We hit areas where
the published documentation is thin so we have to rely on tests
run on the hardware to figure out how things should behave.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we check for valid sub-insns in parallel insns, we can
enable the tests that explicitly validate those code paths.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we keep track of the exact parallel insn slot we're in, we can
make sure that the current insn being decoded is valid for that slot.
This brings us much closer to the hardware in flagging invalid parallel
insn combinations.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some insns need to know which slot they're in to determine whether they
are valid. So add an enum for each slot, and check that rather than the
overall insn len. This makes tracking things in the code much clearer.
However, this code is functionally the same, so a follow up patch will
leverage this more to properly flag invalid parallel insn combos.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we have the se_all helpers together and working, we can see
what pieces are duplicated in each test and unify them in the common
header file.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
