DEFAULT_CRIS_ARCH. Handle crisv32-*-linux-gnu* like
cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
* configure: Regenerate.
* config/tc-cris.c (enum cris_archs): New.
(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
(cris_insn_ver_valid_for_arch): New functions.
(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
(cris_arch): New variable.
(md_pseudo_table): New pseudo .arch.
(err_for_dangerous_mul_placement): Initialize according to
DEFAULT_CRIS_ARCH.
(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
All users changed.
(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
(BRANCH_WF_V32, BRANCH_WB_V32): New.
(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
use in md_cris_relax_table.
(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
Update and improve head comment.
(OPTION_PIC): Define in terms of previous option, OPTION_US.
(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
(OPTION_ARCH): New.
(md_longopts): New option --march=...
(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
macros.
(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
(HANDLE_RELAXABLE): New macro.
(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
cases. Check for weak symbols and assume not relaxable. Handle
STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
STATE_ABS_BRANCH_V32, STATE_LAPC. Use new variable symbolP, not
fragP->fr_symbol.
(md_convert_frag): Handle STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
(cris_create_short_jump): Adjust for CRISv32.
(md_create_long_jump): Ditto. Emit error for common_v10_v32.
(md_begin): Define symbols "..asm.arch.cris.v32",
"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
"..asm.arch.cris.any_v0_v10". Use cris_insn_ver_valid_for_arch
when entering opcode table entry points.
(md_assemble): Adjust branch handling for CRISv32. Handle LAPC
relaxation. In fix_new_exp call for main insn, pass 1 for pcrel
parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
(cris_process_instruction): Initialize out_insnp->insn_type to
CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
cases.
<case 'm'>: Check that modified_char == '.'.
<invalid operands>: Consume the rest of the line.
When operands don't match, skip over subsequent insns with
non-matching version specifier but same mnemonic.
<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
special registers in CRISv32 are always 32 bit long.
<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
New cases.
(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
and compatible. Recognize "ACR" for v32, unless followed by "+".
(get_spec_reg): Consider cris_arch when looking up register.
(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
v32 or compatible.
(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
(cris_get_expression): Restore input_line_pointer if failing "early".
(get_flags): Consider cris_arch and recognize flags accordingly.
(branch_disp): Adjust for CRISv32.
(gen_cond_branch_32): Similar. Emit error for common_v10_v32.
(cris_number_to_imm): Use as_bad_where, not as_bad. Remove
related FIXME. Don't insist on BFD_RELOC_32_PCREL fixup to be
resolved. Don't enter zeros in object file for
BFD_RELOC_32_PCREL.
<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
<case BFD_RELOC_CRIS_SIGNED_8>: New case.
(md_parse_option): Break out "return 1".
<OPTION_ARCH> New case.
(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
<case BFD_RELOC_32_PCREL>: New cases.
Addends for non-zero fx_pcrel are too in fx_offset.
(md_show_usage): Show --march=<arch>.
(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
(s_syntax) <struct syntaxes>: Properly constify member operand.
* config/tc-cris.h (TARGET_MACH): Define.
(cris_mach): Declare.
* doc/as.texinfo (Overview) <CRIS>: Add --march=...
* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
(CRIS-Opts): Document --march=...
(CRIS-Pseudos): Document .arch.
* archures.c (bfd_mach_cris_v0_v10, bfd_mach_cris_v32)
(bfd_mach_cris_v10_v32): New macros.
* cpu-cris.c: Tweak formatting.
(get_compatible): New function.
(N): New macro.
(bfd_cris_arch_compat_v10_v32, bfd_cris_arch_v32): New
bfd_arch_info_type:s.
(bfd_cris_arch): Use bfd_mach_cris_v0_v10 for member mach,
get_compatible for member compatible and link bfd_cris_arch_v32 as
next.
* elf32-cris.c (cris_elf_pcrel_reloc)
(cris_elf_set_mach_from_flags): New functions.
(cris_elf_howto_table) <R_CRIS_8_PCREL, R_CRIS_16_PCREL>
<R_CRIS_32_PCREL>: Use cris_elf_pcrel_reloc.
(cris_elf_grok_prstatus, cris_elf_grok_psinfo): Give correct
numbers for bfd_mach_cris_v32.
(PLT_ENTRY_SIZE_V32): New macro.
(elf_cris_plt0_entry): Drop last comma in initializer.
(elf_cris_plt0_entry_v32, elf_cris_plt_entry_v32)
(elf_cris_pic_plt0_entry_v32, elf_cris_pic_plt_entry_v32): New
PLT initializers.
(cris_elf_relocate_section): Change all "%B(%A)" messages to
"%B, section %A".
(elf_cris_finish_dynamic_symbol): Do V32-specific PLT entries.
(elf_cris_finish_dynamic_sections): Similar.
(elf_cris_adjust_dynamic_symbol): Similar.
(cris_elf_check_relocs): Change all "%B(%A)" messages to "%B,
section %A".
<switch with PIC relocs>: Emit error and return FALSE for
bfd_mach_cris_v10_v32.
<case R_CRIS_8_PCREL, case R_CRIS_16_PCREL, case R_CRIS_32_PCREL>:
Emit warning when generating textrel reloc.
(cris_elf_object_p): Call cris_elf_set_mach_from_flags.
(cris_elf_final_write_processing): Set flags according to mach.
(cris_elf_print_private_bfd_data): Display
EF_CRIS_VARIANT_COMMON_V10_V32 and EF_CRIS_VARIANT_V32.
(cris_elf_merge_private_bfd_data): Drop variables old_flags,
new_flags. Don't call cris_elf_final_write_processing. Don't
look at the actual elf header flags at all; use
bfd_get_symbol_leading_char to check ibfd, obfd. Trap difference
in bfd_get_mach for ibfd and obfd and handle merging of compatible
objects.
(bfd_elf32_bfd_copy_private_bfd_data): Define.
* reloc.c (BFD_RELOC_CRIS_SIGNED_8, BFD_RELOC_CRIS_UNSIGNED_8)
(BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_UNSIGNED_16)
(BFD_RELOC_CRIS_LAPCQ_OFFSET): New relocs.
* bfd-in2.h, libbfd.h: Regenerate.
* cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
(struct cris_disasm_data): New type.
(format_reg, format_hex, cris_constraint, print_flags)
(get_opcode_entry): Add struct cris_disasm_data * parameter. All
callers changed.
(format_sup_reg, print_insn_crisv32_with_register_prefix)
(print_insn_crisv32_without_register_prefix)
(print_insn_crisv10_v32_with_register_prefix)
(print_insn_crisv10_v32_without_register_prefix)
(cris_parse_disassembler_options): New functions.
(bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
parameter. All callers changed.
(get_opcode_entry): Call malloc, not xmalloc. Return NULL on
failure.
(cris_constraint) <case 'Y', 'U'>: New cases.
(bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
for constraint 'n'.
(print_with_operands) <case 'Y'>: New case.
(print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
<case 'N', 'Y', 'Q'>: New cases.
(print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
(print_insn_cris_with_register_prefix)
(print_insn_cris_without_register_prefix): Call
cris_parse_disassembler_options.
* cris-opc.c (cris_spec_regs): Mention that this table isn't used
for CRISv32 and the size of immediate operands. New v32-only
entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
Change brp to be v3..v10.
(cris_support_regs): New vector.
(cris_opcodes): Update head comment. New format characters '[',
']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
Add new opcodes for v32 and adjust existing opcodes to accommodate
differences to earlier variants.
(cris_cond15s): New vector.
comments. Remove member cris_ver_sim. Add members
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
(struct cris_support_reg, struct cris_cond15): New types.
(cris_conds15): Declare.
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
SIZE_FIELD_UNSIGNED.
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
unw_aux_info and unw_table_entry.
(find_symbol_for_address): Pass symtab and strtab info explicitly.
(dump_ia64_unwind): Rename unw_{aux_info,table_entry} with ia64_
prefix.
(slurp_ia64_unwind_table): Likewise.
(ia64_process_unwind): Rename from old process_unwind.
(hppa_unw_aux_info): New.
(dump_hppa_unwind): New.
(slurp_hppa_unwind_table): New.
(hppa_process_unwind): New.
(process_unwind): Factor out common unwinding checks; dispatch to
unwind handler based on machine type.
(mipsnbsd_fetch_inferior_registers): Rename from
fetch_inferior_registers. Make static.
(mipsnbsd_store_inferior_registers): Rename from
store_inferior_registers. Make static.
(_initialize_mipsnbsd_nat): New function and prototype.
* Makefile.in (mipsnbsd-nat.o): Update dependencies.
* config/mips/nbsd.mh (NAT_CLIBS, NAT_FILE): Remove variables.
(NATDEPFILES): Remove infptrace.o and inftarg.o. Add
inf-ptrace.o.
