Commit Graph

25 Commits

Author SHA1 Message Date
Jeff Law 8329699005 * mn10300-opc.c: Add some comments explaining the various
operands and such.

        * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
1996-12-06 22:04:12 +00:00
Jeff Law 23b01150f5 * mn10300-opc.c (mn10300_opcodes): Fix mask field for
mov am,(imm32,sp).
Found during initial simulator work.
1996-11-26 20:28:34 +00:00
Jeff Law 731c7b4bb8 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
opcode.
1996-11-25 19:46:21 +00:00
Jeff Law f039819018 * mn10300-opc.c: Fix handling of register list operand for
"call", "ret", and "rets" instructions.
Stuff noticed while working on disasembler.
1996-11-20 18:32:44 +00:00
Jeff Law aa9c04cd55 * mn10300-dis.c (disassemble): Print PC-relative and memory
addresses symbolically if possible.
        * mn10300-opc.c: Distinguish between absolute memory addresses,
        pc-relative offsets & random immediates.
More disassembler work.
1996-11-20 18:02:31 +00:00
Jeff Law 4aa92185f8 * mn10300-dis.c: Start working on disassembler support.
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes.  Breaks badly if given data instead of
code.  No operands yet.
1996-11-19 23:59:27 +00:00
Jeff Law 99246e03f9 * mn10300-opc.c (mn10300_operands): Add "REGS" for a register
list.
        (mn10300_opcodes): Use REGS for register list in "movm" instructions.
1996-11-19 20:32:31 +00:00
Jeff Law 54dfaf0a65 * mn10300-opc.c (mn10300_opcodes): Demand parens around
register argument is calls and jmp instructions.
Found trying to build libgcc2 for the mn10300 :-)
1996-11-15 20:43:44 +00:00
Jeff Law f2ab9a7505 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
getx operand.  Fix opcode for mulqu imm,dn.
Fix bugs exposed by gas testsuite (extended instructions).
1996-11-07 07:26:25 +00:00
Jeff Law 26433754cc * mn10300-opc.c (mn10300_operands): Hijack "bits" field
in MN10300_OPERAND_SPLIT operands for how many bits
        appear in the basic insn word.  Add IMM32_HIGH24,
        IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
        (mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
1996-11-06 21:58:21 +00:00
Jeff Law 64ce06688d * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
for bset, bclr, btst instructions.
        (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
1996-11-06 21:18:27 +00:00
Jeff Law fdef41f30b * mn10300-opc.c (mn10300_operands): Remove many redundant
operands.  Update opcode table as appropriate.
        (IMM32): Add MN10300_OPERAND_SPLIT flag.
        (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
1996-11-06 20:44:58 +00:00
Jeff Law bb5e141ab4 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
operands (for indexed load/stores).  Fix bitpos for DI
        operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
        few instructions that insert immediates/displacements in the
        middle of the instruction.  Add IMM8E for 8 bit immediate in
        the extended part of an instruction.
        (mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
1996-11-05 20:29:31 +00:00
Jeff Law e85c140a27 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
a data/address register that appears in register field 0
        and register field 1.
        (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Hacking Matsushita again.  Yippie!
1996-11-04 19:51:31 +00:00
Jeff Law 63dc694d29 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
field for movhu instruction.
Bug found by gas testsuite.

        * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
        cast value to "long" not "signed long" to keep hpux10
        compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
1996-10-11 22:06:47 +00:00
Jeff Law ba8ed10c7e * mn10300-opc.c (FMT*): Remove definitions.
Moved into opcode/mn10300.h
1996-10-10 20:31:06 +00:00
Jeff Law 1e5ddd3be4 * mn10300-opc.c (mn10300_opcodes): Fix destination register
for shift-by-register opcodes.
Bug found by testsuite.
1996-10-10 19:08:46 +00:00
Jeff Law 36b34aa4a9 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
into [AD][MN][01] for encoding the position of the register
        in the opcode.
Matsushita.
1996-10-10 16:28:14 +00:00
Jeff Law 344d6417bb * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
1996-10-09 17:20:59 +00:00
Jeff Law db22905430 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
Fix various typos.  Add "PAREN" operand.
        (MEM, MEM2): Define.
        (mn10300_opcodes): Surround all memory addresses with "PAREN"
        operands.  Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
1996-10-08 21:09:57 +00:00
Jeff Law 06b796584d * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
changes.
Matsushita.
1996-10-08 17:56:40 +00:00
Jeff Law 5ab7bce62d * mn10300-opc.c (FMT_XX): Renumber starting at one.
(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
        at this time.
        (mn10300_opcodes): Break opcode format out into its own field.
        Update many operand fields to deal with signed vs unsigned
        issues.  Fix one or two typos in the "mov" instruction
        opcode, mask and/or operand fields.
Checkpointing today's work.  Matsushita.
1996-10-07 22:52:18 +00:00
Jeff Law 99777c0bfb * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
all opcodes.  Very rough cut at operands for all opcodes.
Matsushita.
1996-10-04 22:02:43 +00:00
Jeff Law cd8a9026b9 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the
opcode table.
Checkpointint 10300 work.
1996-10-04 19:20:19 +00:00
Jeff Law ae1b99e42d Grrr. The mn10200 and mn10300 are _not_ similar enough to easily support
with a single generic configuration.  So break them up into two different
configurations.  See the individual ChangeLogs for additional detail.
1996-10-03 16:42:22 +00:00