(ARM_Strong_Prop, STRONGARM): Define.
* arminit.c (ARMul_NewState): Reset is_StrongARM.
(ARMul_SelectProcessor): Set is_StrongARM.
* wrapper.c (sim_create_inferior): Use bfd machine type to
determine processor type to emulate.
* armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
when emulating StrongARM.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC. Moved the existing logic...
(WriteR15Branch): ... here. New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
extracted from state->Cpsr, but preserve the unused bits.
(ARMul_GetCPSR): Get bits preserved in state->Cpsr.
(ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
get the full CPSR word.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
Committed by Elena Zannoni <ezannoni@cygnus.com>
* sh-tdep.c (sh_skip_prologue): Change prologue matching for modern
compilers.
(sh_frame_find_saved_regs): Ditto.
(sh_find_callers_reg): Stop if pc is zero.
* configure.in: Add entry for mips-*-sysv4*MP*
* configure: Rebuild
* config/tc-mips.c (mips_target_format): Return elf32-tradbigmips or
elf32-tradlittlemips for traditional mips targets.
* config/tc-mips.c (md_estimate_size_before_relax): Duplicate the
test for Link Once sections as in adjust_reloc_syms.
* config/te-tmips.h: New file for traditional mips targets. Define
TE_TMIPS.
* config.bfd: Change targ_defvec and targ_selvecs for mips*-*-sysv4*
to add a new target for traditional mips i.e
bfd_elf32_tradbigmips_vec and bfd_elf32_tradlittlemips_vec.
* configure.in: Likewise.
* configure: Rebuild.
* targets.c (bfd_elf32_tradbigmips_vec): Declare and put in
bfd_target_vector.
(bfd_elf32_tradlittlemips_vec): Likewise.
* elfxx-target.h: Add macro INCLUDED_TARGET_FILE which is more a test
to see that elfNN_bed does not get redefined even if the target file
is included twice for a chip. See elf32-mips.c.
Andrew Cagney