gcc:
* config/sh/sh.h (EXTRA_SPECS): Add subtarget_asm_relax_spec and
subtarget_asm_isa_spec.
(SUBTARGET_ASM_RELAX_SPEC, SUBTARGET_ASM_ISA_SPEC): Define.
(ASM_SPEC): Define as SH_ASM_SPEC.
(SH_ASM_SPEC): New; take the role of ASM_SPEC, but safe from svr4.h.
Use subtarget_asm_relax_spec and subtarget_asm_isa_spec.
* config/sh/elf.h (ASM_SPEC): Use SH_ASM_SPEC.
(SUBTARGET_ASM_ISA_SPEC): Undef / define.
gcc/testsuite:
gcc.dg/sh-relax.c: New test.
include/elf:
* sh.h (EF_SH_MERGE_MACH): Make sure SH2E & SH3/SH3E merge to SH3E,
and SH2E & SH4 merge to SH4, not SH2E.
gas:
* config/tc-sh.c (sh_dsp): Replace with preset_target_arch.
(md_begin): Use preset_target_arch.
(md_longopts): Make isa option unconditional.
(md_parse_option): Make OPTION_DSP and OPTION_ISA sh4 / any
set preset_target_arch.
(md_apply_fix3): If BFD_ASSEMBLER, adjust SWITCH_TABLE fixups
by -S_GET_VALUE (fixP->fx_subsy).
(tc_gen_reloc): For SWITCH_TABLE fixups, the symbol is fixp->fx_subsy,
and the addend is 0.
Adjust addend of R_SH_IND12W relocations by fixp->fx_offset - 4.
* config/tc-sh.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
bfd:
elf32-sh.c (sh_elf_howto_tab): Make R_SH_IND12W into an ordinary
relocation (no special function), and make it non-partial_inplace.
(sh_elf_relax_section): When creating a bsr, use a consistent value
no matter if the symbol is extern or not; set addend to -4.
Don't swap load / non-load instructions for SH4.
(sh_elf_relax_delete_bytes): In R_SH_IND12W case, check the offset
rather than if the symbol is external to determine if adjusting the
offset makes sense. Adjust the addend too if appropriate.
(sh_elf_relocate_section): In R_SH_IND12W, don't fiddle with the
relocation.
(SUB_SEGMENT_ALIGN): If HANDLE_ALIGN defined, pad out last frag to
section alignment.
* config/obj-coff.c (SUB_SEGMENT_ALIGN): Likewise.
* config/obj-ieee.c (SUB_SEGMENT_ALIGN): Likewise.
(write_object_file): Invoke md_do_align if available, and use
frag_align_code on text sections.
* config/obj-vms.h (SUB_SEGMENT_ALIGN): Now two args.
* config/tc-m88k.h (SUB_SEGMENT_ALIGN): Likewise.
* config/tc-ppc.h (SUB_SEGMENT_ALIGN): Likewise.
* config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise.
* config/tc-i386.h (SUB_SEGMENT_ALIGN): Likewise. Define for
BFD_ASSEMBLER too.
* Makefile.am (BFD32_BACKENDS): Add elf32-sh-nbsd.lo.
(BFD32_BACKENDS_CFILES): Add elf32-sh-nbsd.c.
(elf32-sh-nbsd.lo): New rule.
* Makefile.in: Regenerate.
* config.bfd (sh*le-*-netbsdelf*): New target.
(sh*-*-netbsdelf*): New target.
* configure.in: Include netbsd-core.lo for native sh*-*-netbsd*.
(bfd_elf32_shnbsd_vec): New vector.
(bfd_elf32_shlnbsd_vec): New vector.
* configure: Regenerate.
* elf32-sh-nbsd.c: New file.
* targets.c: Update copyright years.
(_bfd_target_vector): Add bfd_elf32_shlnbsd_vec and
bfd_elf32_shnbsd_vec.
gas:
* configure.in (sh*le): Set cpu_type=sh and endian=little.
(sh*-*-netbsdelf*): New target.
* configure: Regenerate.
* tc-sh.h: Update copyright years.
(TARGET_FORMAT): Add version for TE_NetBSD.
ld:
* Makefile.am (ALL_EMULATIONS): Add eshelf_nbsd.o and eshlelf_nbsd.o.
(eshelf_nbsd.c): New rule.
(eshlelf_nbsd.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt (sh*le-*-netbsdelf*): New target.
(sh*-*-netbsdelf*): New target.
* emulparams/shelf.sh: Document that shelf_nbsd.sh sources this file.
* ld/emulparams/shelf_nbsd.sh: New emulation.
* ld/emulparams/shlelf_nbsd.sh: New emulation.
* config/tc-sh.c (md_apply_fix): Map 32-bit relocations that
become PC-relative to BFD_RELOC_32_PCREL. Reject 16- or 8-bit
similar relocs.
(sh_obj_adjustable): Return 1 for PC-relative offsets used in
branches.
* config/tc-sh.h (DIFF_EXPR_OK, GLOBAL_OFFSET_TABLE_NAME,
TC_RELOC_GLOBAL_OFFSET_TABLE, TC_RELOC_RTSYM_LOC_FIXUP): Define.
* config/tc-sh.c (sh_elf_cons, sh_elf_suffix): New functions.
[OBJ_ELF] (md_pseudo_table) <long, int, word, short>: Use them.
(GOT_symbol): New variable.
(md_undefined_symbol): Set it.
Reinstate bits of sh4 support that got accidentally deleted.
Add sh-dsp support.
bfd:
* archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros.
(bfd_mach_sh3_dsp): Likewise.
(bfd_mach_sh4): Reinstate.
(bfd_default_scan): Recognize 7410, 7708, 7729 and 7750.
* bfd-in2.h: Regenerate.
* coff-sh.c (struct sh_opcode): flags is no longer short.
(USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros.
(sh_opcode41, sh_opcode42): Integrate as sh_opcode41.
(sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes.
(sh_opcode41, sh_opcode4, sh_opcode80): Likewise.
(sh_opcodes): No longer const.
(sh_dsp_opcodef0, sh_dsp_opcodef): New arrays.
(sh_insn_uses_reg): Check for USESAS and USESR8.
(sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS.
(_bfd_sh_align_load_span): Return early for SH4.
Modify sh_opcodes lookup table for sh-dsp / sh3-dsp.
Take into account that field b of a parallel processing insn
could be mistaken for a separate insn.
* cpu-sh.c (arch_info_struct): New array elements for
sh2, sh-dsp and sh3-dsp.
Reinstate element for sh4.
(SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros.
(SH4_NEXT): Reinstate.
(SH3_NEXT, SH3E_NEXT): Adjust.
* elf-bfd.h (_sh_elf_set_mach_from_flags): Declare.
* elf32-sh.c (sh_elf_set_private_flags): New function.
(sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise.
(sh_elf_merge_private_data): New function.
(elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define.
(bfd_elf32_bfd_copy_private_bfd_data): Define.
(bfd_elf32_bfd_merge_private_bfd_data): Change to
sh_elf_merge_private_data.
gas:
* config/tc-sh.c ("elf/sh.h"): Include.
(sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables.
(md.begin): Initialize target_arch.
Only include opcodes in has table that match selected architecture.
(parse_reg): Recognize register names for sh-dsp.
(parse_at): Recognize post-modify addressing.
(get_operands): The leading space is now optional.
(get_specific): Remove FDREG_N support. Add support for sh-dsp
arguments. Update valid_arch.
(build_Mytes): Add support for SDT_REG_N.
(find_cooked_opcode): New function, broken out of md_assemble.
(assemble_ppi, sh_elf_final_processing): New functions.
(md_assemble): Use find_cooked_opcode and assemble_ppi.
(md_longopts, md_parse_option): New option: -dsp.
* config/tc-sh.h (elf_tc_final_processing): Define.
(sh_elf_final_processing): Declare.
include/elf:
* sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
opcodes:
* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
(print_insn_ppi): Likewise.
(print_insn_shx): Use info->mach to select appropriate insn set.
Add support for sh-dsp. Remove FD_REG_N support.
* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
(sh_arg_type): Likewise. Remove FD_REG_N.
(sh_dsp_reg_nums): New enum.
(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
(arch_sh3_dsp_up): Likewise.
(sh_opcode_info): New field: arch.
(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
D_REG_N. Fill in arch field. Add sh-dsp insns.
Kaz Kojima