ELF section sh_flags SHF_PPC_VLE was being set based on arch/mach,
which meant all code sections in an object file has the flag or all
lacked it. We can do better than that. Only those code sections
where VLE is enabled ought to have the flag, allowing an object file
to contain both VLE and non-VLE code.
Also, ELF header p_flags PF_PPC_VLE wasn't being set, and segments
were being split unnecessarily.
bfd/
* elf32-ppc.c (ppc_elf_section_processing): Delete.
(elf_backend_section_processing): Don't define.
(ppc_elf_modify_segment_map): Set p_flags and mark valid. Don't
split on non-exec sections differing in SHF_PPC_VLE. When
splitting segments, mark size invalid.
gas/
* config/tc-ppc.c (md_assemble): Set sh_flags for VLE. Test
ppc_cpu rather than calling ppc_mach to determine VLE mode.
(ppc_frag_check, ppc_handle_align): Likewise use ppc_cpu.
On i386, IFUNC function must be called via PLT. Since PLT in PIC
object uses EBX register, R_386_PLT32 relocation must be used to
call IFUNC function even when IFUNC function is defined locally.
Linker should issue an error when R_386_PC32 relocation is used
to call IFUNC function.
Since PR ld/19784 tests doesn't use PLT relocation to local IFUNC
function, they are moved to the x86-64 test directory.
bfd/
PR ld/14961
PR ld/20515
* elf32-i386.c (elf_i386_check_relocs): Issue an error when
R_386_PC32 relocation is used to call IFUNC function in PIC
object.
ld/
PR ld/14961
PR ld/20515
* testsuite/ld-i386/i386.exp: Run pr20515.
* testsuite/ld-i386/pr20515.d: New file.
* testsuite/ld-i386/pr20515.s: Likewise.
* testsuite/ld-ifunc/ifunc-14a.s: Use R_386_PLT32 to call IFUNC
function.
* testsuite/ld-ifunc/ifunc-14c.s: Likewise.
* testsuite/ld-ifunc/ifunc-2-i386.s: Likewise.
* testsuite/ld-ifunc/ifunc-2-local-i386.s: Likewise.
* testsuite/ld-ifunc/ifunc.exp: Move PR ld/19784 tests to ...
* testsuite/ld-x86-64/x86-64.exp: Here.
* testsuite/ld-ifunc/pr19784a.c: Moved to ...
* testsuite/ld-x86-64/pr19784a.c: Here.
* testsuite/ld-ifunc/pr19784b.c: Moved to ...
* testsuite/ld-x86-64/pr19784b.c: Here.
* testsuite/ld-ifunc/pr19784c.c: Moved to ...
* testsuite/ld-x86-64/pr19784c.c: Here.
Commit 980aa3e6 was supposed to cure dyn_reloc counting problems, but
did the opposite. For PIC we count two types of dyn_reloc, those on
pc-relative relocs, and the total. If a sym needs pc-relative dyn
relocs then all the relocs are dynamic. If not, then only those that
are must_be_dyn_reloc are dynamic.
PR 20519
* elf64-ppc.c (pc_dynrelocs): New function.
(ppc64_elf_relocate_section): Use it and must_be_dyn_reloc to
handle pic dynamic relocs.
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (struct elf32_arm_params): Define.
(bfd_elf32_arm_set_target_relocs): Rename into ...
(bfd_elf32_arm_set_target_params): This. Use a struct
elf32_arm_params to pass all parameters but the bfd and bfd_link_info.
* bfd-in2.h: Regenerate.
* elf32-arm.c (bfd_elf32_arm_set_target_relocs): Rename into ...
(bfd_elf32_arm_set_target_params): This. Pass all values via a struct
elf32_arm_params rather than as individual parameters.
ld/
* emultempl/armelf.em (params): New static variable.
(thumb_entry_symbol, byteswap_code, target1_is_rel, target2_type,
fix_v4bx, use_blx, vfp11_denorm_fix, stm32l4xx_fix, fix_cortex_a8,
no_enum_size_warning, no_wchar_size_warning, pic_veneer,
merge_exidx_entries, fix_arm1176, cmse_implib): move as part of the
above new structure.
(arm_elf_before_allocation): Access static variable from the params
structure.
(gld${EMULATION_NAME}_finish): Likewise.
(arm_elf_create_output_section_statements): Likewise and pass the
address of that structure to bfd_elf32_arm_set_target_relocs instead
of the static variables.
(PARSE_AND_LIST_ARGS_CASES): Access static variable from the params
structure.
bfd/
* elf32-arm.c (elf32_arm_get_stub_entry): Assert that we don't access
passed the end of htab->stub_group array.
(elf32_arm_create_or_find_stub_sec): Likewise.
(elf32_arm_create_stub): Likewise.
Forgot to set should_relocate to TRUE in case of GOT and TLS relocations of
undefined symbols for shared libraries.
In dynamic libraries if symbol is not known the instruction relocation would
not be resolved to point to the respective .got entry.
A test was created to detect similar future mistakes.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* elf32-arc.c (elf_arc_relocate_section): Changed. Set should_relocate
to TRUE for GOT and TLS relocs.
ld/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* ld/testsuite/ld-arc/tls_gd-01.s: Added a testcase for this patch.
* ld/testsuite/ld-arc/tls_gd-01.d: Likewise.
ARC was overloading this options by forcing DT_INIT AND DT_FINI
to always point to _init and _fini, respectively.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synospsys.com>
* elf32-arc.c (elf_arc_finish_dynamic_sections): Changed.
Fixed conditions related to dynamic relocs relative offset patching.
Added arc_link_hash_table to be able to always generate and track
.rela.bss section.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* elf-bfd.h: Added ARC_ELF_DATA to enum elf_target_id.
* elf32-arc.c (struct elf_arc_link_hash_entry): Added.
(struct elf_arc_link_hash_table): Likewise.
(elf_arc_link_hash_newfunc): Likewise.
(elf_arc_link_hash_table_free): Likewise.
(arc_elf_link_hash_table_create): Likewise.
(elf_arc_relocate_section): Fixed conditions related to dynamic
(elf_arc_check_relocs): Likewise.
(arc_elf_create_dynamic_sections): Added
(elf_arc_adjust_dynamic_symbol): Changed access to .rela.bss to be done
through the hash table.
When no dynamic relocation was generated the .got content would not be
updated for the TLS_IE_GOT relocation addresses.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (relocate_fix_got_relocs_for_got_info): Fixed addresses in
debug comments. Fixed address in .got related to TLS_IE_GOT dynamic
relocation.
ld/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* testsuite/ld-arc/tls_ie-01.s: Added to verify associated fix.
* testsuite/ld-arc/tls_ie-01.d: Likewise
Added support for ARC_SDA_12 reloc.
Fixed ARC_N32_ME.
Added ME (middle-endian) to ARC_SDA_12 reloc.
bfd/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12
relocation.
* bfd-in2.h: Regenerated from the previous changes.
* libbfd.h: Regenerated from the previous changes.
include/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
* opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation.
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* bfd-in.h (bfd_elf32_arm_set_target_relocs): Add a new parameter for
the input import library bfd.
* bfd-in2.h: Regenerate.
* elf32-arm.c (struct elf32_arm_link_hash_table): New in_implib_bfd
and new_cmse_stub_offset fields.
(stub_hash_newfunc): Initialize stub_offset and stub_template_size to
-1.
(elf32_arm_add_stub): Likewise for stub_offset.
(arm_new_stubs_start_offset_ptr): New function.
(arm_build_one_stub): Only allocate a stub_offset if it is -1. Allow
empty SG veneers to have zero relocations.
(arm_size_one_stub): Only initialize stub size and template
information for non empty veneers. Do not update veneer section size
if veneer already has an offset.
(elf32_arm_create_stub): Return the stub entry pointer or NULL instead
of a boolean indicating success or failure.
(cmse_scan): Change stub_changed parameter into an integer pointer
parameter cmse_stub_created to count the number of stub created and
adapt to change of return value in elf32_arm_create_stub.
(cmse_entry_fct_p): New function.
(arm_list_new_cmse_stub): Likewise.
(set_cmse_veneer_addr_from_implib): Likewise.
(elf32_arm_size_stubs): Define cmse_stub_created, pass its address to
cmse_scan instead of that of cmse_stub_changed to compute the number
of stub created and use it to initialize stub_changed. Call
set_cmse_veneer_addr_from_implib after all cmse_scan. Adapt to change
of return value in elf32_arm_create_stub. Use
arm_stub_section_start_offset () if not NULL to initialize size of
secure gateway veneers section. Initialize stub_offset of Cortex-A8
erratum fix to -1. Use ret to hold return value.
(elf32_arm_build_stubs): Use arm_stub_section_start_offset () if not
NULL to initialize size of secure gateway veneers section. Adapt
comment to stress the importance of zeroing veneer section content.
(bfd_elf32_arm_set_target_relocs): Add new in_implib_bfd parameter to
initialize eponymous field in struct elf32_arm_link_hash_table.
ld/
* emultempl/armelf.em (in_implib_filename): Declare and initialize new
variable.
(arm_elf_create_output_section_statements): Open import input library
file for writing and pass resulting in_implib_bfd to
bfd_elf32_arm_set_target_relocs.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_IN_IMPLIB option.
(PARSE_AND_LIST_LONGOPTS): Define --in-implib option.
(PARSE_AND_LIST_OPTIONS): Add help message for --in-implib option.
(PARSE_AND_LIST_ARGS_CASES): Handle new OPTION_IN_IMPLIB case.
* ld.texinfo (--cmse-implib): Update to mention --in-implib.
(--in-implib): Document new option.
* NEWS: Likewise.
* testsuite/ld-arm/arm-elf.exp
(Secure gateway import library generation): add --defsym VER=1 to gas
CLI.
(Secure gateway import library generation: errors): Likewise.
(Input secure gateway import library): New test.
(Input secure gateway import library: no output import library):
Likewise.
(Input secure gateway import library: not an SG input import library):
Likewise.
(Input secure gateway import library: earlier stub section base):
Likewise.
(Input secure gateway import library: later stub section base):
Likewise.
(Input secure gateway import library: veneer comeback): Likewise.
(Input secure gateway import library: entry function change):
Likewise.
* testsuite/ld-arm/cmse-implib.s: Add input import library testing.
* testsuite/ld-arm/cmse-implib.rd: Update accordingly.
* testsuite/ld-arm/cmse-new-implib.out: New file.
* testsuite/ld-arm/cmse-new-implib.rd: Likewise.
* testsuite/ld-arm/cmse-new-implib-no-output.out: Likewise.
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out: Likewise.
* testsuite/ld-arm/cmse-new-earlier-later-implib.out: Likewise.
* testsuite/ld-arm/cmse-new-comeback-implib.rd: Likewise.
* testsuite/ld-arm/cmse-new-wrong-implib.out: Likewise.
This enhances the 32-bit and 64-bit s390 ELF backends with support for
reading and writing the core dump note sections NT_PRSTATUS and
NT_PRPSINFO. Byte swapping is done as appropriate, such that core files
can now be processed correctly on non-s390 platforms.
bfd/ChangeLog:
* elf32-s390.c (stdarg.h): New include.
(elf_s390_grok_psinfo): New function.
(elf_s390_write_core_note): New function.
(elf_backend_grok_psinfo): Declare backend hook.
(elf_backend_write_core_note): Likewise.
* elf64-s390.c (stdarg.h): New include.
(elf_s390_grok_prstatus): New function.
(elf_s390_grok_psinfo): New function.
(elf_s390_write_core_note): New function.
(elf_backend_grok_prstatus): Declare backend hook.
(elf_backend_grok_psinfo): Likewise.
(elf_backend_write_core_note): Likewise.
This patch adds function elf32_arc_grok_parse to parse NOTE section of core
dump files. GDB requires this to work properly with core dumps.
bfd/
2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
* elf32-arc.c (elf32_arc_grok_prstatus): New function.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
The pr19784 tests fail on ppc32 due to a gcc bug. The failure should
be noticed when building both libpr19784a.so and libpr19784b.so,
rather than ld building a buggy libpr19784a.so that fails at run time.
This patch fixes that by moving the @local ifunc check out of
check_relocs, where a call destination may not yet be known to be
ifunc. The patch also adds a related error for -mbss-plt code.
* elf32-ppc.c (ppc_elf_check_relocs): Move error for @local ifunc..
(ppc_elf_relocate_section): ..to here. Comment. Error on
detecting -mbss-plt -fPIC local ifuncs too.
(ppc_elf_size_dynamic_sections): Comment on unnecessary glink
branch table entries.
At the cost of an extra field in the symbol table hash entries, this
simplification to the relocate_section dynamic reloc test should help
maintainability.
* elf64-ppc.c (struct ppc_link_hash_entry): Add weakref.
(ppc64_elf_copy_indirect_symbol): Set weakref. Don't merge
dyn_relocs for weakdefs.
(alias_readonly_dynrelocs): New function.
(ppc64_elf_adjust_dynamic_symbol): Use alias_readonly_dynrelocs.
(ppc64_elf_relocate_section): Simplify condition under which
dyn_relocs are emitted.
This patch fixes quite a lot of confusion in allocate_dynrelocs over
ifuncs. Function descriptors make ELFv1 quite different to ELFv2.
PR 20472
* elf64-ppc.c (ppc64_elf_before_check_relocs): Tweak abiversion test.
(readonly_dynrelocs): Comment fix.
(global_entry_stub): New function.
(ppc64_elf_adjust_dynamic_symbol): Tweak abiversion test. Match
ELFv2 code deciding on dynamic relocs vs. global entry stubs to
that in size_global_entry_stubs, handling ifunc too. Delete dead
weak sym code.
(allocate_dynrelocs): Ensure dyn_relocs field is cleared when no
dyn_relocs are needed. Correct handling of ifunc dyn_relocs.
Tidy ELIMINATE_COPY_RELOCS code, only setting dynindx for
undefweak syms. Expand and correct comments.
(size_global_entry_stubs): Ensure symbol is defined.
(ppc64_elf_relocate_section): Match condition under which
dyn_relocs are emitted to that in allocate_dynrelocs.
Undefined weak functions, like __gmon_start__, were not being made
dynamic or emitting plt call code. While the behaviour of undefined
weak symbols is not defined in the ELF standard, the intention on
powerpc64 was to make it possible to link without a definition of such
symbols and at run time behave the same as if a definition was found
at link time in a shared library.
* elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol): Don't exit with
non_got_ref true in any case where we could have generated dynbss
copies but decide not to do so.
For the case where a function which requires an LA25 stub is at the
beginning of a section we use a short sequence comprised of a LUI/ADDIU
instruction pair only and prepended to the associated function rather
than using a trailing jump to reach the function. This works by
checking for the offset into section of the function symbol being 0.
This is however never the case for microMIPS function symbols, which
have the ISA bit set. Consequently the short LA25 sequence is never
produced for microMIPS functions, like with the following example:
$ cat la25a.s
.abicalls
.global f1
.ent f1
f1:
.set noreorder
.cpload $25
.set reorder
.option pic0
jal f2
.option pic2
jr $31
.end f1
.global f2
.ent f2
f2:
jr $31
.end f2
$ cat la25b.s
.abicalls
.option pic0
.global __start
.ent __start
__start:
jal f1
jal f2
.end __start
$ as -mmicromips -32 -EB -o la25a.o la25a.s
$ as -mmicromips -32 -EB -o la25b.o la25b.s
$ ld -melf32btsmip -o la25 la25a.o la25b.o
$ objdump -d la25
la25: file format elf32-tradbigmips
Disassembly of section .text:
004000d0 <.pic.f2>:
4000d0: 41b9 0040 lui t9,0x40
4000d4: d420 0083 j 400106 <f2>
4000d8: 3339 0107 addiu t9,t9,263
4000dc: 0000 0000 nop
004000e0 <.pic.f1>:
4000e0: 41b9 0040 lui t9,0x40
4000e4: d420 0078 j 4000f0 <f1>
4000e8: 3339 00f1 addiu t9,t9,241
4000ec: 0000 0000 nop
004000f0 <f1>:
4000f0: 41bc 0002 lui gp,0x2
4000f4: 339c 801f addiu gp,gp,-32737
4000f8: 033c e150 addu gp,gp,t9
4000fc: f420 0083 jal 400106 <f2>
400100: 0000 0000 nop
400104: 45bf jrc ra
00400106 <f2>:
400106: 45bf jrc ra
...
00400110 <__start>:
400110: f420 0070 jal 4000e0 <.pic.f1>
400114: 0000 0000 nop
400118: f420 0068 jal 4000d0 <.pic.f2>
40011c: 0000 0000 nop
$
where `.pic.f1' could omit the trailing jump and the filler NOP and just
fall through to `f1'.
Correct the problem by masking out the ISA bit from microMIPS functions,
which fixes the earlier example:
$ objdump -d la25
la25: file format elf32-tradbigmips
Disassembly of section .text:
004000d0 <.pic.f2>:
4000d0: 41b9 0040 lui t9,0x40
4000d4: d420 0083 j 400106 <f2>
4000d8: 3339 0107 addiu t9,t9,263
...
004000e8 <.pic.f1>:
4000e8: 41b9 0040 lui t9,0x40
4000ec: 3339 00f1 addiu t9,t9,241
004000f0 <f1>:
4000f0: 41bc 0002 lui gp,0x2
4000f4: 339c 801f addiu gp,gp,-32737
4000f8: 033c e150 addu gp,gp,t9
4000fc: f420 0083 jal 400106 <f2>
400100: 0000 0000 nop
400104: 45bf jrc ra
00400106 <f2>:
400106: 45bf jrc ra
...
00400110 <__start>:
400110: f420 0074 jal 4000e8 <.pic.f1>
400114: 0000 0000 nop
400118: f420 0068 jal 4000d0 <.pic.f2>
40011c: 0000 0000 nop
$
There is no need to do anything for MIPS16 functions, because if any
LA25 stub has been generated for such a function, then it is only
required for an associated call thunk only, which is regular MIPS code
and the address of which, with the ISA bit clear, is returned by
`mips_elf_get_la25_target'.
This problem has been there since the beginning of microMIPS support:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support").
bfd/
* elfxx-mips.c (mips_elf_add_la25_stub): Clear the ISA bit of
the stub address retrieved if associated with a microMIPS
function.
Fix a problem with missing microMIPS symbol annotation with microMIPS
LA25 stub symbols. The consequence of the issue is these symbols appear
in the symbol table as regular MIPS symbols with the ISA bit set, as
shown with the example below:
$ cat la25a.s
.abicalls
.global f1
.ent f1
f1:
.set noreorder
.cpload $25
.set reorder
.option pic0
jal f2
.option pic2
jr $31
.end f1
.global f2
.ent f2
f2:
jr $31
.end f2
$ cat la25b.s
.abicalls
.option pic0
.global __start
.ent __start
__start:
jal f1
jal f2
.end __start
$ as -mmicromips -32 -EB -o la25a.o la25a.s
$ as -mmicromips -32 -EB -o la25b.o la25b.s
$ ld -melf32btsmip -o la25 la25a.o la25b.o
$ readelf -s la25
Symbol table '.symtab' contains 18 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00400098 0 SECTION LOCAL DEFAULT 1
2: 004000b0 0 SECTION LOCAL DEFAULT 2
3: 004000d0 0 SECTION LOCAL DEFAULT 3
4: 00000000 0 SECTION LOCAL DEFAULT 4
5: 00000000 0 SECTION LOCAL DEFAULT 5
6: 00418110 0 NOTYPE LOCAL DEFAULT 3 _gp
7: 004000e1 16 FUNC LOCAL DEFAULT 3 .pic.f1
8: 004000d1 16 FUNC LOCAL DEFAULT 3 .pic.f2
9: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _fdata
10: 00400110 16 FUNC GLOBAL DEFAULT [MICROMIPS] 3 __start
11: 00400106 2 FUNC GLOBAL DEFAULT [MICROMIPS] 3 f2
12: 004000d0 0 NOTYPE GLOBAL DEFAULT 3 _ftext
13: 00410120 0 NOTYPE GLOBAL DEFAULT 3 __bss_start
14: 004000f0 22 FUNC GLOBAL DEFAULT [MICROMIPS] 3 f1
15: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _edata
16: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _end
17: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _fbss
$
where microMIPS annotation is missing for `.pic.f1' and `.pic.f2' even
though these stubs are associated with microMIPS functions `f1' and `f2'
respectively.
Add the missing annotation then, by copying it from the function symbol
an LA25 stub is associated with, correcting the example above:
$ readelf -s la25
Symbol table '.symtab' contains 18 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00400098 0 SECTION LOCAL DEFAULT 1
2: 004000b0 0 SECTION LOCAL DEFAULT 2
3: 004000d0 0 SECTION LOCAL DEFAULT 3
4: 00000000 0 SECTION LOCAL DEFAULT 4
5: 00000000 0 SECTION LOCAL DEFAULT 5
6: 00418110 0 NOTYPE LOCAL DEFAULT 3 _gp
7: 004000e0 16 FUNC LOCAL DEFAULT [MICROMIPS] 3 .pic.f1
8: 004000d0 16 FUNC LOCAL DEFAULT [MICROMIPS] 3 .pic.f2
9: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _fdata
10: 00400110 16 FUNC GLOBAL DEFAULT [MICROMIPS] 3 __start
11: 00400106 2 FUNC GLOBAL DEFAULT [MICROMIPS] 3 f2
12: 004000d0 0 NOTYPE GLOBAL DEFAULT 3 _ftext
13: 00410120 0 NOTYPE GLOBAL DEFAULT 3 __bss_start
14: 004000f0 22 FUNC GLOBAL DEFAULT [MICROMIPS] 3 f1
15: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _edata
16: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _end
17: 00410120 0 NOTYPE GLOBAL DEFAULT 3 _fbss
$
This problem has been there since the beginning of microMIPS support:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support").
bfd/
* elfxx-mips.c (mips_elf_create_stub_symbol): For a microMIPS
stub also add STO_MICROMIPS annotation.
Fix a linker regression introduced with commit 9d862524f6 ("MIPS:
Verify the ISA mode and alignment of branch and jump targets") causing a
build failure in microMIPS glibc where the `zdump' tool fails to link:
.../timezone/zdump.o: In function `yeartot':
.../timezone/zdump.c:758:(.text+0x62): Jump to a non-instruction-aligned address
.../timezone/zdump.c:758:(.text+0x76): Jump to a non-instruction-aligned address
.../timezone/zdump.c:768:(.text+0x112): Jump to a non-instruction-aligned address
.../timezone/zdump.c:774:(.text+0x1b8): Jump to a non-instruction-aligned address
.../timezone/zdump.c:774:(.text+0x1cc): Jump to a non-instruction-aligned address
collect2: error: ld returned 1 exit status
make[2]: *** [.../timezone/zdump] Error 1
The cause of the failure is the stricter check introduced with the said
change for jump and branch targets tripping on the address of microMIPS
LA25 stubs. Despite being microMIPS code these stubs do not have the
ISA bit set throughout the relocation calculation process, because they
have their address set to the memory offset into the stub section they
are placed in.
The `mips_elf_la25_stub' structure does not carry ISA mode information,
but there is no need to extend it, because the ISA mode can be inferred
from the original symbol, which will have STO_MICROMIPS annotation, so
use that instead to set the ISA bit appropriately. Also only LA25 stubs
associated with microMIPS symbols need to have the ISA bit set, because
other LA25 stubs are made with regular MIPS code, even if associated
with a MIPS16 symbol (in which case they are needed by a call thunk only
rather than the MIPS16 function proper).
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Set the ISA bit
in microMIPS LA25 stub references.
Alan Modra
GDB Administrator
H.J. Lu
Thomas Preud'homme
Cupertino Miranda
Andreas Arnez
Anton Kolesov
Nick Clifton
Maciej W. Rozycki