than s,t. Change div macro to be d,v,t rather than d,s,t.
Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu,
rem and remu which generates only the corresponding div
instruction. This is for compatibility with the MIPS assembler,
which only generates the simple machine instruction when an
explicit destination of $0 is used.
* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
Ian Lance Taylor
Jim Kingdon