James Lemke
5d5a459fd1
Update DMA register addresses
1998-02-11 23:19:52 +00:00
Frank Ch. Eigler
43a6998b41
- PKE simulation code almost complete. Still missing:
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* handling of super duper packed UNPACK arguments
* skipping of in-progress instruction on break/stop
* interrupt generation to 5900
* PATH2/PATH3 status checking & masking
* ability to write to FIFO one word (instead of quadword) at a time
1998-02-11 19:42:15 +00:00
Ian Carmichael
52793fab2f
* Many changes to make sky sim build with --enable-sim-warnings.
1998-02-10 20:08:16 +00:00
Ian Carmichael
dde66fa756
* Make it so vu.bin is an optional file.
1998-02-10 00:13:54 +00:00
Ian Carmichael
2c88fae9ad
* Add hardware_init hook.
1998-02-09 23:53:33 +00:00
Andrew Cagney
452b380811
Fix double dependency for itable.[hc]. Was causing both the mips16 and the
...
normal mips simulators to be built.
1998-02-07 06:24:51 +00:00
Frank Ch. Eigler
fba9bfed2d
- Added almost all code needed for PKE0/1 simulation. Considers
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clarifications given in SCEI question/answer batches #1 and #2 .
1998-02-07 00:12:14 +00:00
Doug Evans
f3534b6867
sky sanitization
1998-02-06 03:27:55 +00:00
Doug Evans
5759734b2c
* Makefile.in (SIM_SKY_OBJS,MIPS_EXTRA_OBJS): New vars.
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(SIM_OBJS): Add $(MIPS_EXTRA_OBJS).
* configure.in: Set mips_extra_objs to sky files if mips64r59*-sky-*.
* configure: Regenerated.
1998-02-06 03:19:56 +00:00
Doug Evans
72db5610de
Prepend sky- to sky header file names.
1998-02-06 03:11:44 +00:00
Doug Evans
803f52b9dc
Second pass at moving sky files into mips dir,
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prepend sky- to all #include's of sky headers.
1998-02-06 03:09:03 +00:00
Doug Evans
aea481da17
First pass at moving sky stuff from ../txvu to mips dir.
1998-02-06 02:29:22 +00:00
Andrew Cagney
8c9ee21e2f
New files, update .Sanitize
1998-02-05 22:08:33 +00:00
Andrew Cagney
37379a256b
IGEN - Replace IMEM (IMEM_IMMED) macro with IMEM<insn-size> macro,
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update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
1998-02-03 05:39:15 +00:00
Andrew Cagney
4634263c4c
Make IGEN the generator for all but mips16 simulators.
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Clean up botched merge in interp.c:sim_open().
1998-02-02 14:14:17 +00:00
Andrew Cagney
a97f304b04
Add support for configuring the size of the floating point unit (fp_word).
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For mips, move fp_registers into a separate array of type fp_word[].
1998-02-02 14:06:52 +00:00
Andrew Cagney
2acd126a47
Rewrite the mipsI/II/III pending-slot code.
1998-02-02 13:49:17 +00:00
Andrew Cagney
192ae475f9
Always compile FP code (test for FP at run-time).
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Remove dependance of interp.c on gencode.c's output.
1998-02-02 08:25:33 +00:00
Andrew Cagney
01737f42d8
mips: Add multi-processor support for r5900. Others might work.
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common, igen: Fix MP related bugs.
1998-02-01 03:29:48 +00:00
Andrew Cagney
412c4e940e
Add config support for the size of the target address and OF cell.
1998-01-31 14:07:23 +00:00
Andrew Cagney
c4db5b04f8
mips - for r5900 generate igen simulator.
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igen - stop crash when simulator isn't multi-sim'ed
1998-01-31 06:56:13 +00:00
Andrew Cagney
9ec6741b17
igen: Fix SMP simulator generator support.
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Use the bfd-processor name in the sim-engine switch.
Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
Update
mips: Fill in bfd-processor field of model records so that
they match ../bfd/archures.
1998-01-31 06:23:41 +00:00
Andrew Cagney
2d44e12a27
Use macro GPR_SET(N,VAL) to clear zero registers.
1998-01-21 22:08:37 +00:00
Doug Evans
462cfbc4eb
* aclocal.m4: Recognize --enable-maintainer-mode.
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*/configure: Regenerated.
1998-01-20 06:37:00 +00:00
Andrew Cagney
13151a934d
Document existence of old (gencode) and new (igen) MIPS ISA simulators.
1998-01-16 01:09:15 +00:00
Mark Alexander
e0e0fc765e
* interp.c (sim_monitor): Handle Densan monitor outbyte
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and inbyte functions.
1998-01-05 23:43:30 +00:00
Felix Lee
76ef416550
* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1997-12-29 16:03:23 +00:00
Andrew Cagney
9c8ec16d78
In nrun.c, look for sigaction & SA_RESTART. When both present,
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install cntrl-c (SIGINT) handler with no SA_RESTART bit set.
1997-12-15 12:33:59 +00:00
Andrew Cagney
b17d2d1474
For MADD et.al. instructions sign extend 32 bit result assigned to a
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register.
1997-12-13 04:23:31 +00:00
Jeff Law
255cbbf190
* configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
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vr5400 with the vr5000 as the default.
1997-12-12 19:24:34 +00:00
Jeff Law
23850e9219
* mips.igen (MSUB): Fix to work like MADD.
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* gencode.c (MSUB): Similarly.
1997-12-11 00:11:04 +00:00
Andrew Cagney
c02ed6a8a3
For bfd, add vr5400 and vr5000 mips machine variants to list of machines.
...
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
1997-12-09 04:01:06 +00:00
Doug Evans
6e51f990a2
Regenerate configure files.
1997-12-04 17:26:06 +00:00
Andrew Cagney
0931ce5aa7
Missing change log entry.
1997-12-03 22:54:44 +00:00
Andrew Cagney
0d5d0d102d
Fix typo in format argument to sim_io_eprintf.
1997-11-26 12:07:27 +00:00
Andrew Cagney
35c246c9d7
Move MDMX instructions which are public knowledge from vr5400.igen
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into mdmx.igen (MDMX is MMX on steroids). Keep the file secret.
1997-11-26 11:47:36 +00:00
Andrew Cagney
8c31916d92
sanitize-r5900 not v5900
1997-11-25 22:02:59 +00:00
Andrew Cagney
58fb5d0a4f
vr5400 sanitize cleanups
1997-11-25 21:47:16 +00:00
Andrew Cagney
9dcdd9ad73
Sanitization
1997-11-24 13:34:52 +00:00
Andrew Cagney
232156dee9
o Add SIM_SIGFPE to sim-signals
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o Start SIM_SIG* at 64 so that the use of host signal numbers can be
detected and reported.
o Update MIPS simulator to use sim-signal.
1997-11-20 09:50:36 +00:00
Andrew Cagney
a09a30d298
Allow reads/writes to C0_CONFIG register.
1997-11-20 09:17:06 +00:00
Doug Evans
486740ce01
* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1997-11-18 23:40:40 +00:00
Andrew Cagney
f23e93dab0
* mips.igen: Tag vr5000 instructions.
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(ANDI): Was missing mipsIV model, fix assembler syntax.
(do_c_cond_fmt): New function.
(C.cond.fmt): Handle mips I-III which do not support CC field
separatly.
(bc1): Handle mips IV which do not have a delaed FCC separatly.
(SDR): Mask paddr when BigEndianMem, not the converse as specified
in IV3.2 spec.
(DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
vr5000 which saves LO in a GPR separatly.
* configure.in (enable-sim-igen): For vr5000, select vr5000
specific instructions.
* configure: Re-generate.
1997-11-14 08:27:38 +00:00
Andrew Cagney
a94c5493a7
Make the signess of compares between GPR's explicit using a cast to
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signed_word.
1997-11-11 12:31:24 +00:00
Andrew Cagney
030843d7f8
Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,
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SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
1997-11-11 07:50:13 +00:00
Andrew Cagney
95469cebdd
Replace global IPC with function argument cia or current instruction
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address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
1997-11-06 14:24:57 +00:00
Andrew Cagney
7ce8b9178c
IGEN likes to cache the current instruction address (CIA). Change the
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MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
1997-11-06 09:16:16 +00:00
Andrew Cagney
44b8585a3d
Add option --enable-sim-igen to mips configuration. Allows user to
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attempt a build of an older MIPS simulator using igen.
1997-11-05 09:43:34 +00:00
Andrew Cagney
63be8febf7
Rewrite the MIPS simulator's memory model so that it uses the generic
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common/sim-core.
Add support for 3, 5, 6, 7 byte transfers to sim core.
1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e
Delete -l and -n options, didn't do anything.
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Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
1997-11-05 01:08:12 +00:00