Commit Graph

11 Commits

Author SHA1 Message Date
Szabolcs Nagy
3d731f6949 [AArch64] Increase max_num_aliases in aarch64-gen
Some ARMv8.3 pointer authentication instructions are encoded as HINT aliases,
so to allow more instruction aliases in the generator, max_num_aliases is
increased from 16 to 32.

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
2016-11-11 10:22:56 +00:00
Richard Sandiford
bd11d5d837 [AArch64][SVE 02/32] Avoid hard-coded limit in indented_print
The maximum indentation needed by aarch64-gen.c grows as more
instructions are added to aarch64-tbl.h.  Rather than having to
increase the indentation limit to a higher value, it seemed better
to replace it with "%*s".

opcodes/
	* aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
2016-09-21 16:48:06 +01:00
Szabolcs Nagy
20f55f3866 Fix generation of AArhc64 instruction table.
* aarch64-gen.c (VERIFIER): Define.
	* aarch64-opc.c (VERIFIER): Define.
	(verify_ldpsw): Use static linkage.
	* aarch64-opc.h (verify_ldpsw): Remove.
	* aarch64-tbl.h: Use VERIFIER for verifiers.
2016-05-03 11:48:56 +01:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Matthew Wahab
a0f7013add [AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.

Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d
2015-12-11 10:12:08 +00:00
Matthew Wahab
35822b3812 [AArch64] Let aliased instructions be their preferred form.
Although the AArch64 backend supports aliased instructions, the aliasing
forms are always preferred over the real instruction. This makes it
awkward to handle instructions which have aliases but which are their
own preferred form.

This patch includes the instruction being aliased in the list of
alternatives which is searched when considering which form to use.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c: Weaken assert.
	* aarch64-gen.c: Include the instruction in the list of its
	possible aliases.

Change-Id: I1f23eb25fccef76a64d3d732d58761bd25fad94e
2015-11-27 15:05:09 +00:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Yufeng Zhang
e30181a58d include/opcode/
2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.

opcodes/

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

gas/testsuite/

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* gas/aarch64/alias.s: Add new tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
2013-01-30 15:43:32 +00:00
Nick Clifton
a06ea96464 Add support for 64-bit ARM architecture: AArch64 2012-08-13 14:52:54 +00:00