Commit Graph

9173 Commits

Author SHA1 Message Date
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
2020-01-16 14:33:01 +00:00
Jan Beulich
45a4bb2010 x86: drop found_cpu_match local variable
50aecf8c5f could have done so right away; perhaps the variable shouldn't
have been introduced in the first place.
2020-01-16 10:07:36 +01:00
Jan Beulich
4814632e69 x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).

For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
2020-01-16 10:05:35 +01:00
Jozef Lawrynowicz
131cb553d6 MSP430: Fix relocation overflow when using #lo(EXP) macro
gas/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X
	relocations when the target is 430X, except when extracting part of an
	expression.
	(msp430_srcoperand): Adjust comment.
	Initialize the expp member of the msp430_operand_s struct as
	appropriate.
	(msp430_dstoperand): Likewise.
	* testsuite/gas/msp430/msp430.exp: Run new test.
	* testsuite/gas/msp430/reloc-lo-430x.d: New test.
	* testsuite/gas/msp430/reloc-lo-430x.s: New test.

include/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* opcode/msp430.h (enum msp430_expp_e): New.
	(struct msp430_operand_s): Add expp member to struct.

ld/ChangeLog:

2020-01-15  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* testsuite/ld-msp430-elf/msp430-elf.exp: Run new test.
	* testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-15 13:23:06 +00:00
Alan Modra
c24d0e8d48 Reinstate gas em=freebsd for sparc-freebsd
In commit c9098af41e I over-simplified the sparc target decoding,
missing the fact that prior to that patch sparc-*-freebsd fell through
to the generic *-*-freebsd match.

	* configure.tgt: Add sparc-*-freebsd case.
2020-01-15 16:25:10 +10:30
Lili Cui
e44925ae56 x86: Updated align branch tests for Darwin and i686-pc-elf
1. Update align branch assembler tests to match Darwin disassembler
outputs.
2. Skip unsupported "call *foo" tests in 64-bit mode on Darwin.
3. Update align branch linker test to match any addresses for i686-pc-elf.

gas/

	* testsuite/gas/i386/align-branch-1a.d: Updated for Darwin.
	* testsuite/gas/i386/align-branch-1b.d: Likewise.
	* testsuite/gas/i386/align-branch-1c.d: Likewise.
	* testsuite/gas/i386/align-branch-1d.d: Likewise.
	* testsuite/gas/i386/align-branch-1e.d: Likewise.
	* testsuite/gas/i386/align-branch-1f.d: Likewise.
	* testsuite/gas/i386/align-branch-1g.d: Likewise.
	* testsuite/gas/i386/align-branch-1h.d: Likewise.
	* testsuite/gas/i386/align-branch-1i.d: Likewise.
	* testsuite/gas/i386/align-branch-5.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1i.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
	* testsuite/gas/i386/i386.exp: Skip x86-64-align-branch-2a,
	x86-64-align-branch-2b and x86-64-align-branch-2c on Darwin.

ld/

	* testsuite/ld-i386/align-branch-1.d: Updated for i686-pc-elf.
2020-01-14 08:59:37 -08:00
Sergey Belyashov
7a6bf3becb Fix various assembler testsuite failures for the Z80 target.
PR 25377
gas	* config/tc-z80.c: Add support for half precision, single
	precision and double precision floating point values.
	* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
	* doc/as.texi: Add new z80 command line options.
	* doc/c-z80.texi: Document new z80 command line options.
	* testsuite/gas/z80/ez80_pref_dis.s: New test.
	* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
	* testsuite/gas/z80/z80.exp: Run the new test.
	* testsuite/gas/z80/fp_math48.d: Use correct command line option.
	* testsuite/gas/z80/fp_zeda32.d: Likewise.
	* testsuite/gas/z80/strings.d: Update expected output.

opcodes	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.
2020-01-14 13:13:57 +00:00
Matthew Malcomson
82e9597c9e [gas][aarch64] Turn on SVE when using f32mm or f64mm extensions
There are no instructions under these matrix multiply extensions that
can be used without having SVE enabled.
Since these extensions require SVE, we make that explicit in the options
table.

Tested on aarch64-none-elf without regressions.

gas/ChangeLog:

2020-01-13  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (f64mm, f32mm): Add sve as a feature
	dependency.
2020-01-13 15:31:39 +00:00
Claudiu Zissulescu
5e4f7e0518 [ARC][committed] Code cleanup and improvements.
Code clean up and improvements when changing the cpu from command
line. Also, remove unused/old emulations.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
	the CPU.
	* config/tc-arc.h: Add header if/defs.
	* testsuite/gas/arc/pseudos.d: Improve matching pattern.

ls/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* Makefile.am: Remove earcelf_prof.c and earclinux_prof.c
	emulations.
	* Makefile.in: Regenerate.
	* configure.tgt: Likewise.
	* emulparams/arcelf_prof.sh: Remove file.
	* emulparams/arclinux_prof.sh: Likewise.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (C_NE): Make it required.
2020-01-13 11:16:47 +02:00
Alan Modra
febda64f15 ubsan: wasm32: signed integer overflow
The signed integer overflow occurred when adding one to target_count
  for (i = 0; i < target_count + 1; i++)
but that's the least of the worries here.  target_count was long and i
int, leading to the possibility of a loop that never ended.

So to avoid this type of vulnerability, this patch uses what I believe
to be the proper types for arguments of various wasm32 opcodes, rather
than using "long" which may change in size.

gas/
	* testsuite/gas/wasm32/allinsn.d: Update expected output.
opcodes/
	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.
2020-01-13 16:44:27 +10:30
Alan Modra
5496abe1c5 tic4x: sign extension using shifts
Don't do that.  Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long.  Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.

include/
	* opcode/tic4x.h (EXTR): Delete.
	(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
	extension using shifts.  Do trim INSERTU value to specified bitfield.
opcodes/
	* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
	* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
	insertion.
2020-01-13 12:12:05 +10:30
Alan Modra
ec4181f289 HPUX gas testsuite fixes
* testsuite/gas/elf/pr14891.s: Don't start directives in first column.
	* testsuite/gas/elf/pr21661.d: Don't run on hpux.
2020-01-10 17:32:33 +10:30
Sergey Belyashov
40c75bc8b0 Fix compile time warnings about comparisons always being false.
PR 25224
gas	* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
	opcode byte values.
	(emit_ld_r_r): Likewise.
	(emit_ld_rr_m): Likewise.
	(emit_ld_rr_nn): Likewise.

opcodes	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.
2020-01-09 11:49:18 +00:00
Jan Beulich
72aea32839 x86: refine when to trigger optimizations
Checking just the base opcode without also checking this isn't a VEX
encoding, and without there being other insn properties avoiding a match
once respective VEX/XOP/EXEX-encoded insns would appear, is at least
dangerous. Add respective checks. At the same time there's no real need
to check the extension opcode to be None for the 0xA8 form - there's
nothing it can be confused with, and non-VEX-and-alike forms also can't
appear.
2020-01-09 11:40:04 +01:00
Jan Beulich
3f93af6141 x86-64: assert sane internal state for REX conversions
For the comments about "hi" registers to be really applicable, RegRex
may not be set on the respective registers. Assert this is the case.
2020-01-09 11:39:33 +01:00
Jan Beulich
7697afb662 x86: consistently convert to byte registers for TEST w/ imm optimization
Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.
2020-01-09 11:38:59 +01:00
Jan Beulich
d835a58baa x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD
The disassembler change is such that in default mode we'd disassemble
the insns (for there not ebing any conflicts), but when AMD64 mode was
explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
Nick Clifton
915808f652 Document the fact that the assembler's alignment pseudo-ops can be issued without any argumemtns.
PR 25284
	* doc/as.texi (Align): Document the fact that all arguments can be
	omitted.
	(Balign): Likewise.
	(P2align): Likewise.
2020-01-08 17:00:54 +00:00
Nick Clifton
f1f28025c3 Make the assembler generate an error if there is an attempt to define a section with the same name as an already defined symbol.
PR 14891
	* config/obj-elf.c (obj_elf_section): Fail if the section name is
	already defined as a different symbol type.
	* testsuite/gas/elf/pr14891.s: New test source file.
	* testsuite/gas/elf/pr14891.d: New test driver.
	* testsuite/gas/elf/pr14891.s: New test expected error output.
	* testsuite/gas/elf/elf.exp: Run the new test.
2020-01-08 16:30:20 +00:00
Alan Modra
030a2e78ac ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.

opcodes/
	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.
gas/
	* config/tc-z8k.c (md_begin): Make idx unsigned.
	(get_specific): Likewise for this_index.
2020-01-08 21:51:32 +10:30
Claudiu Zissulescu
2a1ebfb221 [ARC] Improve parsing instruction operands.
We use gas' expression function to parse the operands of an
instruction in a generic way. There are situations when we have labels
and registers having the same name as well as the substraction sign
doesn't always stands for the arithmetical operation but for the
register range (e.g. enter instruction). This patch improves parsing
symbols found in a instruction operand, cleans up code and avoids
using default or undefined variables.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (parse_reloc_symbol): New function.
	(tokenize_arguments): Clean up, use parse_reloc_symbol function.
	(md_operand): Set X_md to absent.
	(arc_parse_name): Check for X_md.
2020-01-07 15:29:31 +02:00
Sergey Belyashov
16d8767399 Allow individual targets to decide if string escapes should be allowed. Disable for PPC and Z80.
PR 25311
	* as.h (TC_STRING_ESCAPES): Provide a default definition.
	* app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of
	NO_STRING_ESCAPES.
	* read.c (next_char_of_string): Likewise.
	* config/tc-ppc.h (TC_STRING_ESCAPES): Define.
	* config/tc-z80.h (TC_STRING_ESCAPES): Define.
2020-01-03 16:23:19 +00:00
Nick Clifton
a2322019f5 Updated Swedish translation for the GAS subdirectory. 2020-01-03 12:59:54 +00:00
Jan Beulich
5437a02abc Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
Jan Beulich
567dfba2be Arm64: correct {su,us}dot SIMD encodings
According to the specification these permit the Q bit to control the
vector length operated on, and hence this bit should not already be set
in the opcode table entries (it rather needs setting dynamically). Note
how the test case output did also not match its input. Besides
correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
Jan Beulich
8c45011acd Arm64: correct uzp{1,2} mnemonics
According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
Jan Beulich
f4950f76fa Arm64: correct 64-bit element fmmla encoding
There's just one bit of difference to the 32-bit element form, as
per the documentation.
2020-01-03 10:12:49 +01:00
Sergey Belyashov
6655dba246 Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.
PR 25224
bfd	* Makefile.am: Add z80-elf target support.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
	* elf32-z80.c: New file.
	* archures.c: Add new z80 architectures: eZ80 and Z180.
	* coffcode.h: Likewise.
	* cpu-z80.c: Likewise.
	* bfd-in2.h: Likewise plus additional Z80 relocations.
	* coff-z80.c: Add new relocations for Z80 target and local label check.

gas	* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
	for assembler code generated by SDCC. Add new relocation types. Add
	z80-elf target support.
	* config/tc-z80.h: Add z80-elf target support. Enable dollar local
	labels. Local labels starts from ".L".
	* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
	* testsuite/gas/all/fwdexp.s: Likewise.
	* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
	* testsuite/gas/z80/z80.exp: Add new tests
	* testsuite/gas/z80/dollar.d: New file.
	* testsuite/gas/z80/dollar.s: New file.
	* testsuite/gas/z80/ez80_adl_all.d: New file.
	* testsuite/gas/z80/ez80_adl_all.s: New file.
	* testsuite/gas/z80/ez80_adl_suf.d: New file.
	* testsuite/gas/z80/ez80_isuf.s: New file.
	* testsuite/gas/z80/ez80_z80_all.d: New file.
	* testsuite/gas/z80/ez80_z80_all.s: New file.
	* testsuite/gas/z80/ez80_z80_suf.d: New file.
	* testsuite/gas/z80/r800_extra.d: New file.
	* testsuite/gas/z80/r800_extra.s: New file.
	* testsuite/gas/z80/r800_ii8.d: New file.
	* testsuite/gas/z80/r800_z80_doc.d: New file.
	* testsuite/gas/z80/z180.d: New file.
	* testsuite/gas/z80/z180.s: New file.
	* testsuite/gas/z80/z180_z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.s: New file.
	* testsuite/gas/z80/z80_ii8.d: New file.
	* testsuite/gas/z80/z80_ii8.s: New file.
	* testsuite/gas/z80/z80_in_f_c.d: New file.
	* testsuite/gas/z80/z80_in_f_c.s: New file.
	* testsuite/gas/z80/z80_op_ii_ld.d: New file.
	* testsuite/gas/z80/z80_op_ii_ld.s: New file.
	* testsuite/gas/z80/z80_out_c_0.d: New file.
	* testsuite/gas/z80/z80_out_c_0.s: New file.
	* testsuite/gas/z80/z80_reloc.d: New file.
	* testsuite/gas/z80/z80_reloc.s: New file.
	* testsuite/gas/z80/z80_sli.d: New file.
	* testsuite/gas/z80/z80_sli.s: New file.

ld	* Makefile.am: Add new target z80-elf
	* configure.tgt: Likewise.
	* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
	* emulparams/elf32z80.sh: New file.
	* emultempl/z80elf.em: Likewise.
	* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180.d: Likewise.
	* testsuite/ld-z80/labels.s: Likewise.
	* testsuite/ld-z80/relocs.s: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/z80.exp: Likewise.

opcodes	* z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 14:14:59 +00:00
Szabolcs Nagy
a65b5de624 [ARM][gas] fix build breakage with gcc-10 by using correct enum type
Fixes

../../gas/config/tc-arm.c: In function 'parse_reg_list':
../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion]
 1946 |        reg = arm_reg_parse (&str, REGLIST_RN);
      |                                   ^~~~~~~~~~

gas/ChangeLog:

	* config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of
	REGLIST_RN.
2020-01-02 13:07:37 +00:00
Alan Modra
b14ce8bfe1 Re: Update year range in copyright notice of binutils files
Add the ChangeLog entry.
2020-01-01 18:55:18 +10:30
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra
0b11474080 ChangeLog rotation 2020-01-01 18:12:08 +10:30
Jan Beulich
f2810fe00a x86: adjust ignored prefix warning for branches
There's no reason to not also issue them in Intel syntax mode, and it
can be quite helpful to mention the actual insn (after all there can be
multiple on a single line).
2019-12-27 09:39:58 +01:00
Jan Beulich
6cb0a70ef3 x86-64: correct / adjust prefix emission
First and foremost REX must come last. Next JumpInterSegment branches
can't possibly have a REX prefix, as they're consistently CpuNo64. And
finally make BND prefix handling in output_branch() consistent with that
of other prefixes in the same function, and make its placement among
prefixes consistent with output_jump() (which, oddly enough, still isn't
the supposedly canonical order specified by the *_PREFIX definitions).
2019-12-27 09:39:17 +01:00
Jan Beulich
376cd05610 x86-64: fix Intel64 handling of branch with data16 prefix
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).

Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.

A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
2019-12-27 09:38:34 +01:00
Jan Beulich
48bcea9f48 x86: consolidate Disp<NN> handling a little
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
  size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
  solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.

This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.

This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).

These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.

Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
  correct Disp8 there (compensated by i386_finalize_displacement()
  now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.

Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
2019-12-27 09:22:03 +01:00
Alan Modra
5b660084e2 Remove tic80 support
This is one way of fixing ubsan bug reports, just delete the code.

The assembler support was removed back in 2005 along with other
non-BFD assemblers, but somehow the remainder of the port stayed in.

bfd/
	* coff-tic80.c: Delete file.
	* cpu-tic80.c: Delete file.
	* archures.c: Remove tic80 support.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* targets.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove tic80 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* doc/as.texi: Remove mention of tic80.
include/
	* coff/tic80.h: Delete file.
	* opcode/tic80.h: Delete file.
ld/
	* emulparams/tic80coff.sh: Delete file.
	* scripttempl/tic80coff.sc: Delete file.
	* configure.tgt: Remove tic80 support.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* tic80-dis.c: Delete file.
	* tic80-opc.c: Delete file.
	* disassemble.c: Remove tic80 support.
	* disassemble.h: Likewise.
	* Makefile.am: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-12-17 16:36:54 +10:30
H.J. Lu
ac0ab1842d i386: Also check R12-R15 registers when optimizing testq to testb
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX
prefix for the low byte register when optimizing

test $imm7, %r64/%r32/%r16 -> test $imm7, %r8

	PR gas/25274
	* config/tc-i386.c (optimize_encoding): Also check R12-R15
	registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8"
	optimization.
	* testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test
	with r12.
	* testsuite/gas/i386/x86-64-optimize-3.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
2019-12-12 12:31:26 -08:00
H.J. Lu
8493b6651a i386: Add tests for -malign-branch-boundary and -malign-branch
Add tests for -malign-branch-boundary, -malign-branch and
-mbranches-within-32B-boundaries.

gas/

	* testsuite/gas/i386/align-branch-1.s: New file.
	* testsuite/gas/i386/align-branch-1a.d: Likewise.
	* testsuite/gas/i386/align-branch-1b.d: Likewise.
	* testsuite/gas/i386/align-branch-1c.d: Likewise.
	* testsuite/gas/i386/align-branch-1d.d: Likewise.
	* testsuite/gas/i386/align-branch-1e.d: Likewise.
	* testsuite/gas/i386/align-branch-1f.d: Likewise.
	* testsuite/gas/i386/align-branch-1g.d: Likewise.
	* testsuite/gas/i386/align-branch-1h.d: Likewise.
	* testsuite/gas/i386/align-branch-2.s: Likewise.
	* testsuite/gas/i386/align-branch-2a.d: Likewise.
	* testsuite/gas/i386/align-branch-2b.d: Likewise.
	* testsuite/gas/i386/align-branch-2c.d: Likewise.
	* testsuite/gas/i386/align-branch-3.d: Likewise.
	* testsuite/gas/i386/align-branch-3.s: Likewise.
	* testsuite/gas/i386/align-branch-4.s: Likewise.
	* testsuite/gas/i386/align-branch-4a.d: Likewise.
	* testsuite/gas/i386/align-branch-4b.d: Likewise.
	* testsuite/gas/i386/align-branch-5.d: Likewise.
	* testsuite/gas/i386/align-branch-5.s: Likewise.
	* testsuite/gas/i386/align-branch-6.d: Likewise.
	* testsuite/gas/i386/align-branch-6.s: Likewise.
	* testsuite/gas/i386/align-branch-7.d: Likewise.
	* testsuite/gas/i386/align-branch-7.s: Likewise.
	* testsuite/gas/i386/align-branch-8.d: Likewise.
	* testsuite/gas/i386/align-branch-8.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-2.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-2a.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-2b.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-3.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-3.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-4.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-4a.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-4b.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-6.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-7.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-7.s: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-8.d: Likewise.
	* testsuite/gas/i386/x86-64-align-branch-8.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run new tests.

ld/

	* testsuite/ld-i386/align-branch-1.d: New file.
	* testsuite/ld-i386/align-branch-1.s: Likewise.
	* testsuite/ld-x86-64/align-branch-1.d: Likewise.
	* testsuite/ld-x86-64/align-branch-1.3: Likewise.
	* testsuite/ld-i386/i386.exp: Run the new test.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
2019-12-12 12:03:45 -08:00
H.J. Lu
76cf450b4c i386: Add -mbranches-within-32B-boundaries
Add -mbranches-within-32B-boundaries to enable

-malign-branch-boundary=32
-malign-branch=jcc+fused+jmp
-malign-branch-prefix-size=5

	* config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New.
	(md_longopts): Add -mbranches-within-32B-boundaries.
	(md_parse_option): Handle -mbranches-within-32B-boundaries.
	(md_show_usage): Add -mbranches-within-32B-boundaries.
2019-12-12 12:03:45 -08:00
H.J. Lu
e379e5f385 i386: Align branches within a fixed boundary
Add 3 command-line options to align branches within a fixed boundary
with segment prefixes or NOPs:

1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align.
The supported branches are:
  a. Conditional jump.
  b. Fused conditional jump.
  c. Unconditional jump.
  d. Call.
  e. Ret.
  f. Indirect jump and call.
3. -malign-branch-prefix-size=NUM aligns branches with NUM segment
prefixes per instruction.

3 new rs_machine_dependent frag types are added:

1. BRANCH_PADDING.  The variable size frag to insert NOP before branch.
2. BRANCH_PREFIX.  The variable size frag to insert segment prefixes to
an instruction.  The choices of prefixes are:
   a. Use the existing segment prefix if there is one.
   b. Use CS segment prefix in 64-bit mode.
   c. In 32-bit mode, use SS segment prefix with ESP/EBP base register
   and use DS segment prefix without ESP/EBP base register.
3. FUSED_JCC_PADDING.  The variable size frag to insert NOP before fused
conditional jump.

The new rs_machine_dependent frags aren't inserted if the previous item
is a prefix or a constant directive, which may be used to hardcode an
instruction, since there is no clear instruction boundary.  Segment
prefixes and NOP padding are disabled before relaxable TLS relocations
and tls_get_addr calls to keep TLS instruction sequence unchanged.

md_estimate_size_before_relax() and i386_generic_table_relax_frag() are
used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.
i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix
and NOP to align the next branch frag:

1. First try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be
inserted before a branch.

	* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
	(tls_get_addr): New.
	(last_insn): New.
	(align_branch_power): New.
	(align_branch_kind): New.
	(align_branch_bit): New.
	(align_branch): New.
	(MAX_FUSED_JCC_PADDING_SIZE): New.
	(align_branch_prefix_size): New.
	(BRANCH_PADDING): New.
	(BRANCH_PREFIX): New.
	(FUSED_JCC_PADDING): New.
	(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
	(md_begin): Abort if align_branch_prefix_size <
	MAX_FUSED_JCC_PADDING_SIZE.
	(md_assemble): Set last_insn.
	(maybe_fused_with_jcc_p): New.
	(add_fused_jcc_padding_frag_p): New.
	(add_branch_prefix_frag_p): New.
	(add_branch_padding_frag_p): New.
	(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
	BRANCH_PREFIX frag and terminate each frag to align branches.
	(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
	relaxable TLS relocations.
	(output_imm): Likewise.
	(i386_next_non_empty_frag): New.
	(i386_next_jcc_frag): New.
	(i386_classify_machine_dependent_frag): New.
	(i386_branch_padding_size): New.
	(i386_generic_table_relax_frag): New.
	(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
	FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
	(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
	FUSED_JCC_PADDING frags.
	(OPTION_MALIGN_BRANCH_BOUNDARY): New.
	(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
	(OPTION_MALIGN_BRANCH): New.
	(md_longopts): Add -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(md_parse_option): Handle -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(md_show_usage): Display -malign-branch-boundary=,
	-malign-branch-prefix-size= and -malign-branch=.
	(i386_target_format): Set tls_get_addr.
	(i386_cons_align): New.
	* config/tc-i386.h (i386_cons_align): New.
	(md_cons_align): New.
	(i386_generic_table_relax_frag): New.
	(md_generic_table_relax_frag): New.
	(i386_tc_frag_data): Add u, padding_address, length,
	max_prefix_length, prefix_length, default_prefix, cmp_size,
	classified and branch_type.
	(TC_FRAG_INIT): Initialize u, padding_address, length,
	max_prefix_length, prefix_length, default_prefix, cmp_size,
	classified and branch_type.
	* doc/c-i386.texi: Document -malign-branch-boundary=,
	-malign-branch= and -malign-branch-prefix-size=.
2019-12-12 12:03:45 -08:00
H.J. Lu
b65d68b8d6 gas: Add md_generic_table_relax_frag
Add md_generic_table_relax_frag for TC_GENERIC_RELAX_TABLE targets so
that a backend can extend relax_frag beyond TC_GENERIC_RELAX_TABLE.

	* write.c (md_generic_table_relax_frag): New.  Defined to
	relax_frag if not defined.
	(relax_segment): Call md_generic_table_relax_frag instead of
	relax_frag.
2019-12-12 12:03:45 -08:00
Alan Modra
4f7cc14110 gas signed overflow fixes
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow.
	* config/tc-metag.c (parse_dalu): Likewise.
	* config/tc-tic4x.c (md_pcrel_from): Likewise.
	* config/tc-tic6x.c (tic6x_output_unwinding): Likewise.
	* config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer.
	Don't use register keyword.  Avoid signed overflow and remove now
	unneccesary char masks.  Formatting.
	* config/tc-ia64.c (operand_match): Don't use shifts to sign extend.
	* config/tc-mep.c (mep_apply_fix): Likewise.
	* config/tc-pru.c (md_apply_fix): Likewise.
	* config/tc-riscv.c (load_const): Likewise.
	* config/tc-nios2.c (md_apply_fix): Likewise.  Don't potentially
	truncate fixup before right shift.  Tidy BFD_RELOC_NIOS2_HIADJ16
	calculation.
2019-12-12 21:58:33 +10:30
Alan Modra
84bc4ba816 obj-evax.c tidy
This started out as fixing decode_16, which used a char to index a 256
byte decodings array.  When char is signed that could result in an out
of bounds array access.  The rest of the patch is for consistency and
just general cleanup.

	* config/obj-evax.c (crc32, encode_32, encode_16, decode_16):
	Remove unnecessary prototypes.
	(number_of_codings): Delete, use ARRAY_SIZE instead throughout.
	(codings, decodings): Make arrays of unsigned char.
	(crc32): Use unsigned variables.  Delete unnecessary mask.
	(encode_32, encode_16): Return unsigned char*, and make static
	buffer an unsigned char array.
	(decode_16): Make arg an unsigned char*.  Remove useless casts.
	(shorten_identifier): Use unsigned char crc_chars.
	(is_truncated_identifier): Make ptr an unsigned char*.
2019-12-12 21:58:23 +10:30
Andre Vieira
24f19ccb89 [gas][arm] Add -mwarn-restrict-it
Add a -m{no-}warn-restrict-it option to control IT related warnings in
ARMv8-A and ARMv8-R.  This is disabled by default.

Committed on behalf of Wilco Dijkstra.

gas/ChangeLog:
2019-12-11  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/tc-arm.c (warn_on_restrict_it): Add new variable.
	(it_fsm_post_encode): Check warn_on_restrict_it.
	(arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.
	* testsuite/gas/arm/armv8-a-bad.d: Likewise.
	* testsuite/gas/arm/armv8-a-it-bad.d: Likewise.
	* testsuite/gas/arm/armv8-r-bad.d: Likewise.
	* testsuite/gas/arm/armv8-r-it-bad.d: Likewise.
	* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.
	* testsuite/gas/arm/udf.d: Likewise.
2019-12-11 15:53:26 +00:00
Jan Beulich
569d50f1c6 x86: further refine SSE check (SSE4a, SHA, GFNI)
In  ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went
both a little too far and not quite far enough:
- GFNI insns also have AVX512 variants, which also shouldn't get
  diagnosed,
- SSE4a insns should get diagnosed just like SSE4.x ones,
- SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
2019-12-11 09:42:29 +01:00
Andre Vieira
0e7aaa728d [gas][arm] Set context table for '.arch_extension'
This patch fixes .arch_extension behaviour.

Currently, context table for '.arch_extension' is only set while
"-march" processing, but it is not set while .arch processing,
so following code is rejected

  .syntax unified
  .thumb
  .arch armv8.1-m.main
  .arch_extension mve.fp

  unless -march=armv8.1-m.main is given.

Committing on behalf of Vladimir Murzin

gas/ChangeLog:
2019-12-10  Vladimir Murzin  <vladimir.murzin@arm.com>

	* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
	* testsuite/gas/arm/mve-arch-ext.s: New.
	* testsuite/gas/arm/mve-arch-ext.d: New.
2019-12-10 16:10:17 +00:00
Jan Beulich
7456d03d5b x86/Intel: fold "xmmword" with "oword"
These are full aliases of one another, so there's no real need to use
distinct O_md* values for them.
2019-12-09 13:32:11 +01:00
Jan Beulich
f2f5811f76 x86/Intel: support "mmword ptr"
This is an alias of "qword ptr", commonly used with MMX insns.

At this occasion also test (alongside the newly supported "mmword")
- "zmmword" used as expression,
- PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09 13:31:39 +01:00
Jan Beulich
164d49cb1c x86/Intel: fix "near ptr" / "far ptr" handling
Commit dc2be329b9 ("i386: Only check suffix in instruction mnemonic")
broke rejecting of these for floating point insns. Fix this by setting
the "byte" operand attribute, which will now (again) cause an error.

Furthermore the diagnostic for the "far ptr" case in general and for the
"near ptr" case in the non-float cases became "invalid instruction
suffix" instead of the intended "operand size mismatch". Fix this by
also setting the "tbyte" operand attribute (no insn template accepts
both byte and tbyte operands).
2019-12-09 13:31:07 +01:00