OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
53,911 Commits 5 Branches 0 Tags 450 MiB
7833670643
Commit Graph

1063 Commits

Author SHA1 Message Date
Nathan Sidwell
7833670643 gas/ 
* config/m68k-parse.h (RAMBAR_ALT): New.
	* config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New.
	(mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl,
	mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl,
	mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl,
	mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for
	RAMBAR1.
	(mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT.
	(m68k_cpus): Adjust 5206, 5206e & 5307 entries.
	(m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used.  Add it
	to control register mapping.

	gas/testsuite/
	* gas/m68k/ctrl-1.d, gas/m68k/ctrl-1.s: New.
	* gas/m68k/ctrl-2.d, gas/m68k/ctrl-2.s: New.
	* gas/m68k/all.exp: Add them.

	opcodes/
	* m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
	rambar1.
 2007-04-20 14:09:00 +00:00
Alan Modra
b84bf58af1 include/opcode/ 
* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
	(num_powerpc_operands): Declare.
	(PPC_OPERAND_SIGNED et al): Redefine as hex.
	(PPC_OPERAND_PLUS1): Define.
opcodes/
	* ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
	change.
	* ppc-opc.c (powerpc_operands): Replace bit count with bit mask
	in all entries.  Add PPC_OPERAND_SIGNED to DE entry.  Remove
	references to following deleted functions.
	(insert_bd, extract_bd, insert_dq, extract_dq): Delete.
	(insert_ds, extract_ds, insert_de, extract_de): Delete.
	(insert_des, extract_des, insert_li, extract_li): Delete.
	(insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
	(insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
	(num_powerpc_operands): New constant.
	(XSPRG_MASK): Remove entire SPRG field.
	(powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
gas/
	* messages.c (as_internal_value_out_of_range): Extend to report
	errors for values with invalid low bits set.
	* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
	fields.  Check that operands and opcode fields are disjoint.
	(ppc_insert_operand): Check operands using mask rather than bit
	count.   Check low bits too.  Handle PPC_OPERAND_PLUS1.  Adjust
	insertion code.
	(md_apply_fix): Adjust for struct powerpc_operand change.
 2007-04-20 12:25:15 +00:00
Alan Modra
0bbdef9222 * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift. 
(Z2_MASK): Define.
	(powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
 2007-04-20 10:24:37 +00:00
Richard Earnshaw
86ad2a1353 * arm-dis.c (print_insn): Only look for a mapping symbol in the section 
being disassembled.
 2007-04-20 00:00:21 +00:00
H.J. Lu
f6fdceb738 Correct SSE4.2 ChangeLog entry. 2007-04-19 17:08:56 +00:00
Alan Modra
a33e055d81 .. 2007-04-19 10:52:48 +00:00
Alan Modra
360b160092 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc, 
db10cyc, db12cyc, db16cyc.
 2007-04-19 01:39:31 +00:00
Alan Modra
b20ae55eff * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe. 2007-04-18 23:57:01 +00:00
H.J. Lu
381d071fc5 gas/ 
2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
	(match_template): Handle operand size for crc32 in SSE4.2.
	(process_suffix): Handle operand type for crc32 in SSE4.2.
	(output_insn): Support SSE4.2.

gas/testsuite/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2.

	* gas/i386/sse4_2.d: New file.
	* gas/i386/sse4_2.s: Likewise.
	* gas/i386/x86-64-sse4_2.d: Likewise.
	* gas/i386/x86-64-sse4_2.s: Likewise.

opcodes/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (CRC32_Fixup): New.
	(PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
	 PREGRP91): New.
	(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
	(threebyte_0x3a_uses_DATA_prefix): Likewise.
	(prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
	PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
	(three_byte_table): Likewise.

	* i386-opc.c (i386_optab): Add SSE4.2 opcodes.

	* gas/config/tc-i386.h (CpuSSE4_2): New.
	(CpuSSE4): Likewise.
	(CpuUnknownFlags): Add CpuSSE4_2.
 2007-04-18 16:15:55 +00:00
H.J. Lu
42903f7f59 gas/ 
2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .sse4.1.
	(process_operands): Adjust implicit operand for blendvpd,
	blendvps and pblendvb in SSE4.1.
	(output_insn): Support SSE4.1.

gas/testsuite/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.

	* gas/i386/sse4_1.d: New file.
	* gas/i386/sse4_1.s: Likewise.
	* gas/i386/x86-64-sse4_1.d: Likewise.
	* gas/i386/x86-64-sse4_1.s: Likewise.

opcodes/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (XMM_Fixup): New.
	(Edqb): New.
	(Edqd): New.
	(XMM0): New.
	(dqb_mode): New.
	(dqd_mode): New.
	(PREGRP39 ... PREGRP85): New.
	(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
	(threebyte_0x3a_uses_DATA_prefix): Likewise.
	(prefix_user_table): Add PREGRP39 ... PREGRP85.
	(three_byte_table): Likewise.
	(putop): Handle 'K'.
	(intel_operand_size): Handle dqb_mode, dqd_mode):
	(OP_E): Likewise.
	(OP_G): Likewise.

	* i386-opc.c (i386_optab): Add SSE4.1 opcodes.

	* i386-opc.h (CpuSSE4_1): New.
	(CpuUnknownFlags): Add CpuSSE4_1.
	(regKludge): Update comment.
 2007-04-18 16:13:15 +00:00
Daniel Jacobowitz
ee5c21a00e 2007-04-18 Matthias Klose <doko@ubuntu.com> 
* Makefile.am (libbfd_la_LDFLAGS): Use bfd soversion.
	(bfdver.h): Use the date in non-release builds for the soversion.
	* Makefile.in: Regenerate.

2007-04-18  Matthias Klose  <doko@ubuntu.com>

	* Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion.
	* Makefile.in: Regenerate.
 2007-04-18 12:14:50 +00:00
Steve Ellcey
b7d19ba641 * Makefile.am: Add ACLOCAL_AMFLAGS. 
* Makefile.in: Regenerate.
 2007-04-14 20:45:09 +00:00
H.J. Lu
6e26e51a85 Remove trailing white spaces. 2007-04-13 21:59:35 +00:00
H.J. Lu
246c51aaae 2007-04-13 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c: Remove trailing white spaces.
 2007-04-13 21:57:21 +00:00
H.J. Lu
7967e09e27 2007-04-11 H.J. Lu <hongjiu.lu@intel.com> 
PR binutils/4333
	* i386-dis.c (GRP1a): New.
	(GRP1b ... GRPPADLCK2): Update index.
	(dis386): Use GRP1a for entry 0x8f.
	(mod, rm, reg): Removed. Replaced by ...
	(modrm): This.
	(grps): Add GRP1a.
 2007-04-11 21:56:25 +00:00
Kazu Hirata
56dc1f8ac3 * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and 
info->print_address_func if longjmp is called.
 2007-04-09 17:09:56 +00:00
DJ Delorie
144f4bc66d * m32c.cpu (Imm-8-s4n): Fix print hook. 
(Lab-24-8, Lab-32-8, Lab-40-8): Fix.
(arith-jnz-imm4-dst-defn): Make relaxable.
(arith-jnz16-imm4-dst-defn): Fix encodings.

* m32c-desc.c: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-opc.c: Regenerate.

* config/tc-m32c.c (rl_for, relaxable): Protect argument.
(md_relax_table): Add entries for ADJNZ macros.
(M32C_Macros): Add ADJNZ macros.
(subtype_mappings): Add entries for ADJNZ macros.
(insn_to_subtype): Check for adjnz and sbjnz insns.
(md_estimate_size_before_relax): Pass insn to insn_to_subtype.
(md_convert_frag): Convert adjnz and sbjnz.
 2007-03-29 23:56:39 +00:00
H.J. Lu
e72cf3ec8e gas/ 
2007-03-28  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_modrm_byte): For instructions with 2
	register operands, encode destination in i.rm.regmem if its
	RegMem bit is set.

opcodes/

2007-03-28  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
	movq.  Remove InvMem from sldt, smsw and str.

	* i386-opc.h (InvMem): Renamed to ...
	(RegMem): Update comments.
	(AnyMem): Remove InvMem.
 2007-03-29 04:27:54 +00:00
H.J. Lu
831480e942 Fix year. 2007-03-27 22:45:19 +00:00
Paul Brook
b74ed8f52a 2006-03-27 Paul Brook <paul@codesourcery.com> 
opcodes/
	* arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
 2007-03-27 21:09:53 +00:00
Paul Brook
4146fd53c0 2007-03-24 Paul Brook <paul@codesourcery.com> 
opcodes/
	* arm-dis.c (coprocessor_opcodes): Remove superfluous 0x.
	(print_insn_coprocessor): Handle %<bitfield>x.
 2007-03-24 02:51:28 +00:00
Paul Brook
b67020158a 2007-03-24 Paul Brook <paul@codesourcery.com> 
Mark Shinwell  <shinwell@codesourcery.com>

	gas/
	* config/tc-arm.c (operand_parse_code): Add OP_oRRw.
	(parse_operands): Don't expect comma if first operand missing.
	Handle OP_oRRw.
	(do_srs): Encode register number, checking it is r13.  Update comment.
	(insns): Update SRS entries to take a register.

	gas/testsuite/
	* gas/arm/archv6.s: Add new SRS tests.
	* gas/arm/archv6.d: Update expected output.
	* gas/arm/thumb32.s: Add new SRS tests.
	* gas/arm/thumb32.d: Update expected output.
	* gas/arm/srs-t2.d: New.
	* gas/arm/srs-t2.l: New.
	* gas/arm/srs-t2.s: New.
	* gas/arm/srs-arm.d: New.
	* gas/arm/srs-arm.l: New.
	* gas/arm/srs-arm.s: New.

	opcodes/
	* arm-dis.c (arm_opcodes): Print SRS base register.
 2007-03-24 01:29:00 +00:00
H.J. Lu
0003779b5d gas/ 
2003-03-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_begin): Allow '.' in mnemonic.

gas/testsuite/

2003-03-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/rex.s: Add tests for rex.WRXB.
	* gas/i386/rex.d: Updated.

	* gas/i386/rex.d: Replace rex64XYZ with rex.WRXB.
	* gas/i386/x86-64-io-intel.d : Likewise.
	* gas/i386/x86-64-io-suffix.d: Likewise.
	* gas/i386/x86-64-io.d: Likewise.
	* gas/i386/x86-64-opcode.d: Likewise.

opcodes/

2003-03-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB.

	* i386-opc.c (i386_optab): Add rex.wrxb.
 2007-03-23 16:17:21 +00:00
H.J. Lu
161a04f630 gas/ 
2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY
	and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.

include/opcode/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (REX_MODE64): Renamed to ...
	(REX_W): This.
	(REX_EXTX): Renamed to ...
	(REX_R): This.
	(REX_EXTY): Renamed to ...
	(REX_X): This.
	(REX_EXTZ): Renamed to ...
	(REX_B): This.

opcodes/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REX_MODE64): Remove definition.
	(REX_EXTX): Likewise.
	(REX_EXTY): Likewise.
	(REX_EXTZ): Likewise.
	(USED_REX): Use REX_OPCODE instead of 0x40.
	Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
	REX_R, REX_X and REX_B respectively.
 2007-03-21 21:23:44 +00:00
H.J. Lu
8b38ad713b gas/ 
2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/4218
	* config/tc-i386.c (match_template): Properly handle 64bit mode
	"xchg %eax, %eax".

gas/testsuite/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/4218
	* gas/i386/nops.s: Add testcases for nop r/m.
	* gas/i386/x86-64-nops.s: Likewise.

	* gas/i386/x86-64-opcode.s: Add testcases for xchg with %ax,
	%eax and %rax.

	* gas/i386/nops.d: Updated.
	* gas/i386/x86-64-nops.d: Likewise.
	* gas/i386/x86-64-opcode.d: Likewise.

opcodes/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/4218
	* i386-dis.c (PREGRP38): New.
	(dis386): Use PREGRP38 for 0x90.
	(prefix_user_table): Add PREGRP38.
	(print_insn): Set uses_REPZ_prefix to 1 for pause.
	(NOP_Fixup1): Properly handle REX bits.
	(NOP_Fixup2): Likewise.

	* i386-opc.c (i386_optab): Allow %eax with xchg in 64bit.
	Allow register with nop.
 2007-03-21 20:45:14 +00:00
DJ Delorie
75b06e7b7a * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, 
mem20): New.
(src16-16-20-An-relative-*): New.
(dst16-*-20-An-relative-*): New.
(dst16-16-16sa-*): New
(dst16-16-16ar-*): New
(dst32-16-16sa-Unprefixed-*): New
(jsri): Fix operands.
(setzx): Fix encoding.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.h: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
 2007-03-21 02:53:50 +00:00
H.J. Lu
c3fe08facb gas/ 
2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_begin): Use i386_regtab_size to scan
	i386_regtab.
	(parse_register): Use i386_regtab_size instead of ARRAY_SIZE
	on i386_regtab.

opcodes/

2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.c: Include "libiberty.h".
	(i386_regtab): Remove the last entry.
	(i386_regtab_size): New.
	(i386_float_regtab_size): Likewise.

	* i386-opc.h (i386_regtab_size): New.
	(i386_float_regtab_size): Likewise.
 2007-03-15 17:30:31 +00:00
H.J. Lu
0b1cf022c8 gas/ 
2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerated.

	* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
	"opcode/i386.h".
	(md_begin): Check reg_name != NULL for the last entry in
	i386_regtab.

	* config/tc-i386.h: Move many entries to opcode/i386.h and
	opcodes/i386-opc.h.

	* configure.in (need_opcodes): Set true for i386.
	* configure: Regenerated.

include/opcode/

2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h: Add entries from config/tc-i386.h and move tables
	to opcodes/i386-opc.h.

opcodes/

2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am (CFILES): Add i386-opc.c.
	(ALL_MACHINES): Add i386-opc.lo.
	Run "make dep-am".
	* Makefile.in: Regenerated.

	* configure.in: Add i386-opc.lo for bfd_i386_arch.
	* configure: Regenerated.

	* i386-dis.c: Include "opcode/i386.h".
	(MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
	(FWAIT_OPCODE): Remove definition.
	(UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
	(MAX_OPERANDS): Remove definition.

	* i386-opc.c: New file.
	* i386-opc.h: Likewise.
 2007-03-15 14:31:24 +00:00
H.J. Lu
56eced12bf 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> 
* Makefile.in: Regenerated.
 2007-03-15 14:20:32 +00:00
H.J. Lu
6f74c397de 2007-03-09 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (OP_Rd): Renamed to ...
	(OP_R): This.
	(Rd): Updated.
	(Rm): Likewise.
 2007-03-09 23:22:31 +00:00
Alan Modra
1620f33de1 Regenerate. 2007-03-08 11:14:20 +00:00
Alan Modra
a6d04ec4ce * Makefile.am: Run "make dep-am". 
* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
 2007-03-08 05:36:12 +00:00
Martin Schwidefsky
b5639b37c5 2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com> 
* opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
	INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU,	INSTR_RRR_F0FF): New
	instruction formats added.
	(MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
	MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
	masks added.
	* opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
	instructions added.
	* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
	(main): z9-ec cpu type option added.
	* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.

2007-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/tc-s390.c (md_parse_option): z9-ec option added.

2007-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>

	* gas/s390/zarch-z9-ec.d: New file.
	* gas/s390/zarch-z9-ec.s: New file.
	* gas/s390/s390.exp: Run the z9-ec testcases.
 2007-03-06 13:19:08 +00:00
DJ Delorie
b2e818b70d * s390-opc.c (INSTR_SS_L2RDRD): New. 
(MASK_SS_L2RDRD): New.
* s390-opc.txt (pka): Use it.

* gas/s390/esa-g5.s: Adjust for corrected PKA syntax.
* gas/s390/esa-g5.d: Adjust for corrected PKA syntax.
 2007-02-22 21:01:59 +00:00
Thiemo Seufer
8b082fb134 [ gas/ChangeLog ] 
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
	(macro_build): Add case '2'.
	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
	(validate_mips_insn): Add support for balign instruction.
	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
	command line options.
	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
	.set dspr2, .set nodspr2.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
	DSP R2.
	* gas/mips/mips.exp: Run new test.

	[ include/opcode/Changelog ]
	* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
	(INSN_DSPR2): Add flag for DSP R2 instructions.
	(M_BALIGN): New macro.

	[ opcodes/ChangeLog ]
	* mips-dis.c (mips_arch_choices): Add DSP R2 support.
	(print_insn_args): Add support for balign instruction.
	* mips-opc.c (D33): New shortcut for DSP R2 instructions.
	(mips_builtin_opcodes): Add DSP R2 instructions.

	[ sim/mips/ChangeLog ]
	* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
	* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
	Add dsp2 to sim_igen_machine.
	* configure: Regenerate.
	* dsp.igen (do_ph_op): Add MUL support when op = 2.
	(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
	(mulq_rs.ph): Use do_ph_mulq.
	(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
	* mips.igen: Add dsp2 model and include dsp2.igen.
	(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
	for *mips32r2, *mips64r2, *dsp.
	(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
	for *mips32r2, *mips64r2, *dsp2.
	* dsp2.igen: New file for MIPS DSP REV 2 ASE.

	[ sim/testsuite/sim/mips/ChangeLog ]
	* basic.exp: Run the dsp2 test.
	* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
	* mips32-dsp2.s: New test.
 2007-02-20 13:28:56 +00:00
Martin Schwidefsky
929e4d1a15 2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com> 
* s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
	(INSTR_RRF_U0RF, MASK_RRF_U0RF): Added.
	* s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr,
	cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF.

2007-02-19  Andreas Krebbel  <krebbel1@de.ibm.com>

        * gas/s390/esa-g5.d (cfxbr, cfebr, cfdbr): Exchanged floating
	point and fixed point operands.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/zarch-z900.d (cfdr, cfer, cfxr, cgdbr, cgebr, cgxbr,
	cgdr, cger, cgxr): Likewise.
	* gas/s390/zarch-z900.s: Likewise.
 2007-02-19 17:46:11 +00:00
Martin Schwidefsky
b8e558488c 2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com> 
* s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type.
	* s390-opc.c (s390_operands): Add RO_28 as optional gpr.
	(INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
	and sfpc.
 2007-02-19 17:29:37 +00:00
Nick Clifton
af69206070 PR binutils/4045 
* avr-dis.c (comment_start): New variable, contains the prefix to use when
    printing addresses in comments.
  (print_insn_avr): Set comment_start to an empty space if there is no symbol
     table available as the generic address printing code will prefix the
     numeric value of the address with 0x.
 2007-02-16 10:24:48 +00:00
H.J. Lu
ce518a5f27 2007-02-13 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c: Updated to use an array of MAX_OPERANDS operands
	 in struct dis386.
 2007-02-13 20:58:17 +00:00
Dave Brolley
8c9c183d15 Fix entries for MeP submission. 2007-02-06 19:51:33 +00:00
Dave Brolley
bd2f2e55ad 2007-02-05 Dave Brolley <brolley@redhat.com> 
* mep-*: New support for Toshiba Media Processor (MeP).
        * Makefile.am: Add support for MeP.
        * configure.in: Likewise.
        * disassemble.c: Likewise.
        * Makefile.in: Regenerated.
        * configure: Regenerated.
 2007-02-05 20:04:22 +00:00
H.J. Lu
eb7834a66d Fix year in entries. 2007-02-05 19:37:12 +00:00
H.J. Lu
65ca155d27 ld/testsuite/ 
2076-02-05  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-i386/pcrel16.d: Undo the last change.
	* ld-x86-64/pcrel16.d: Likewise.

opcodes/

2076-02-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_J): Undo the last change. Properly handle 64K
	wrap around within the same segment in 16bit mode.
 2007-02-05 18:22:49 +00:00
H.J. Lu
206717e8e5 ld/testsuite/ 
2076-02-02  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-i386/pcrel16.d: Updated.
	* ld-x86-64/pcrel16.d: Likewise.

opcodes/

2076-02-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_J): Mask to 16bit only if there is a data16
	prefix.
 2007-02-03 00:46:22 +00:00
H.J. Lu
c4f5c3d74c 2007-02-02 H.J. Lu <hongjiu.lu@intel.com> 
* avr-dis.c (avr_operand): Correct PR number in comment.
 2007-02-02 22:54:50 +00:00
H.J. Lu
fc523535b3 Fix typos in year. 2007-02-02 22:15:52 +00:00
H.J. Lu
f59a29b99f binutils/ 
2076-02-02  H.J. Lu  <hongjiu.lu@intel.com>

	* doc/binutils.texi (objdump): Document the new addr64 option
	for i386 disassembler.

include/

2076-02-02  H.J. Lu  <hongjiu.lu@intel.com>

	* dis-asm.h (print_i386_disassembler_options): New.

opcodes/

2076-02-02  H.J. Lu  <hongjiu.lu@intel.com>

	* disassemble.c (disassembler_usage): Call
	print_i386_disassembler_options for i386 disassembler.

	* i386-dis.c (print_i386_disassembler_options): New.
	(print_insn): Support the new addr64 option.
 2007-02-02 15:27:04 +00:00
Nick Clifton
64a3a6fcf9 * ppc-dis.c (powerpc_dialect): Handle ppc440. 
* ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can be used.
 2007-02-02 12:37:41 +00:00
Alan Modra
ba4e851b3a * ppc-opc.c (insert_bdm): -Many comment. 
(valid_bo): Add "extract" param.  Accept both powerpc and power4
	BO fields when disassembling with -Many.
	(insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call.
 2007-02-02 01:24:43 +00:00
H.J. Lu
10a2343ede Move 2006 ChangeLog entries to ChangeLog-2006. 2007-01-09 14:29:31 +00:00