The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.
The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.
To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.
The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.
A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.
In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense. The asserts were both like this:
gdb_assert (TYPE_LENGTH (ainfo->type)
<= (cinfo->flen + cinfo->xlen));
And were made in two cases, when passing structures like these:
struct {
integer field1;
float field2;
};
or,
struct {
float field1;
integer field2;
};
When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding). In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.
This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC. The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.
Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.
gdb/ChangeLog:
* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
Delete.
<operator==>: Update with for removed field.
<hash>: Likewise.
* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
<isa_features>: ...this.
<abi_features>: New field.
(riscv_isa_flen): Update comment.
(riscv_abi_xlen): New declaration.
(riscv_abi_flen): New declaration.
* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
isa_features.
(riscv_abi_xlen): New function.
(riscv_isa_flen): Update to get answer from isa_features.
(riscv_abi_flen): New function.
(riscv_has_fp_abi): Update to get answer from abi_features.
(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
xlen and flen.
(riscv_call_info) <xlen, flen>: Update comment.
(riscv_call_arg_struct): Remove invalid assertions
(riscv_features_from_gdbarch_info): Update now hw_float_abi field
is removed.
(riscv_gdbarch_init): Gather isa features and abi features
separately, ensure both match on the gdbarch when reusing an old
gdbarch. Relax an error check to allow 32-bit abi float to run on
a target with 64-bit float hardware.
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
Provide a mapping between GDB's register numbers and DWARF's register
numbers. This resolves some failures that I was seeing on
gdb.base/store.exp when running on an rv64imfdc target.
gdb/ChangeLog:
* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
(riscv_gdbarch_init): Register new function with gdbarch.
* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
Make riscv_isa_flen available to the linux native code, and clean up duplicate
comments.
gdb/
* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
(riscv_isa_flen): Likewise. Drop static.
* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
(riscv_isa_flen): Likewise.
A 64-bit FP register can hold either a single or double float value, so
print it as both types by using a union type for FP registers. Likewise
for 128-bit regs which can also hold long double.
gdb/
* riscv-tdep.c (riscv_fpreg_d_type, riscv_fpreg_q_type): New.
(riscv_register_type): Use them.
(riscv_print_one_register_info): Handle union of floats same as float.
* riscv-tdep.h (struct gdbarch_tdep): Add riscv_fpreg_d_type and
riscv_fpreg_q_type fields.
Collects information during the prologue scan and uses this to unwind
registers when no DWARF information is available.
This patch has been tested by disabling the DWARF stack unwinders, and
running the complete GDB testsuite against a range of RISC-V targets.
The results are comparable to running with the DWARF unwinders in
place.
gdb/ChangeLog:
* riscv-tdep.c: Add 'prologue-value.h' include.
(struct riscv_unwind_cache): New struct.
(riscv_debug_unwinder): New global.
(riscv_scan_prologue): Update arguments, capture register details
from prologue scan.
(riscv_skip_prologue): Reformat arguments line, move end of
prologue calculation into riscv_scan_prologue.
(riscv_frame_cache): Update return type, create
riscv_unwind_cache, scan the prologue, and fill in remaining cache
details.
(riscv_frame_this_id): Use frame id computed in riscv_frame_cache.
(riscv_frame_prev_register): Use the trad_frame within the
riscv_unwind_cache.
(_initialize_riscv_tdep): Add 'set/show debug riscv unwinder'
flag.
This fixes some minor formatting issues in riscv-tdep.h, including one
pointed out by ARI.
ChangeLog
2018-08-09 Tom Tromey <tom@tromey.com>
* riscv-tdep.h: Minor formatting fixes.
This adds software single step support that is needed by the linux native port.
This is modeled after equivalent code in the MIPS port.
This also fixes a few bugs in the compressed instruction decode support. Some
instructions are RV32/RV64 specific, and this wasn't being checked. Also, a
few instructions were accidentally using the non-compressed is_* function.
This has been tested on a HiFive Unleashed running Fedora, by putting a
breakpoint on start, typing stepi, and then holding down the return key until
it finishes, and observing that I see everything I expect to see along the way.
There is a problem in _dl_addr where I get into an infinite loop, but it seems
to be some synchronization code that doesn't agree with single step, so I have
to find the end of the loop, put a breakpoint there, continue, and then single
step again until the end.
gdb/
* riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
(decode_register_index_short): New.
(decode_j_type_insn, decode_cj_type_insn): New.
(decode_b_type_insn, decode_cb_type_insn): New.
(riscv_insn::decode): Add support for jumps, branches, lr, and sc. New
local xlen. Check xlen when decoding ambiguous compressed insns. In
compressed decode, use is_c_lui_insn instead of is_lui_insn, and
is_c_sw_insn instead of is_sw_insn.
(riscv_next_pc, riscv_next_pc_atomic_sequence): New.
(riscv_software_single_step): New.
* riscv-tdep.h (riscv_software_single_step): Declare.
This allows the function to be used from riscv OS files, which also need to
depend on XLEN size.
gdb/
* riscv-tdep.c (riscv_isa_xlen): Drop static.
* riscv-tdep.h (riscv_isa_xlen): Add extern declaration.
The GDB coding standard states these lines should never have been
added.
gdb/ChangeLog:
* riscv-tdep.c: Remove 'Contributed by ...' lines from header
comment.
* riscv-tdep.h: Likewise.
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
Andrew Burgess
Joel Brobecker
Jim Wilson
Tom Tromey