* config/tc-ia64.c (md): Add member "loc_directive_seen".
(dot_loc): New function.
(md_pseudo_table): Add entry to map .loc to dot_loc().
(emit_one_bundle): Only call dwarf2_gen_line_info() if we have
seen a .loc directive or we're generating DWARF2 debug info for
assembly source.
* config/tc-sh64.c (shmedia_md_apply_fix3): Add missing
BFD_RELOC_SH_IMMS10BY8 relocation.
* config/tc-sh64.c (shmedia_build_Mytes): Emit an error message rather
than just ignoring bad code.
* v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
bfd/
* reloc.c (BFD_RELOC_V850_LO16_SPLIT_OFFSET): New bfd_reloc_code_type.
* elf32-v850.c (v850_elf_howto_table): Add entry for
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_reloc_map): Map it to BFD_RELOC_V850_LO16_SPLIT_OFFSET.
(v850_elf_perform_lo16_relocation): New function, extracted from...
(v850_elf_perform_relocation): ...here. Use it to handle
R_V850_LO16_SPLIT_OFFSET.
(v850_elf_check_relocs, v850_elf_final_link_relocate): Handle
R_V850_LO16_SPLIT_OFFSET.
* libbfd.h, bfd-in2.h: Regenerate.
gas/
* config/tc-v850.c (handle_lo16): New function.
(v850_reloc_prefix): Use it to check lo().
(md_assemble, md_apply_fix3): Handle BFD_RELOC_V850_LO16_SPLIT_OFFSET.
gas/testsuite/
* gas/v850/split-lo16.{s,d}: New test.
* gas/v850/v850.exp: Run it.
ld/testsuite/
* ld-v850: New directory.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* config/obj-elf.c (obj_elf_change_section): Only set type and
attributes on new sections. Emit warning when type of re-declared
section doesn't match.
gas/testsuite/
2004-12-15 Jan Beulich <jbeulich@novell.com>
* gas/elf/section5.[els]: New.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* dw2gencfi.c (dot.cfi.startproc): Clear cur_cfa_offset so
'.cfi_startproc simple' doesn't inherit the old value.
2004-12-15 Jan Beulich <jbeulich@novell.com>
* dw2gencfi.c (output_cfi_insn): Adjust DW_CFA_def_cfa_sf generation
to emit a signed and factored offset. Adjust DW_CFA_def_cfa_offset_sf
generation to emit a factored offset.
* elfcode.h (elf_slurp_symbol_table): Use bfd_elf_sym_name so that
canonical sections syms have a name.
gas/testsuite/
Update for changed section syms.
ld/testsuite/
Update for changed section syms.
* gas/mips/elf-rel23b.d: New test.
* gas/mips/elf-rel25.s: New test.
* gas/mips/elf-rel25.d: New test.
* gas/mips/elf-rel25a.d: New test.
* gas/mips/mips.exp: Run new tests.
* configure.in: Use it for arm*-*-linux-gnueabi*.
* config/tc-arm.c: Allow emulation file to set FPU_DEFAULT.
* config/te-armlinuxeabi.h: New file.
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* configure: Likewise.
* doc/Makefile.in: Regenerated.
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
They should be correct now.
* gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions.
* gas/mn10300/relax.d: Add expected relocations.
2004-11-23 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
indicate the MMX extensions added by both SSE and 3DNow!A.
(Cpu3dnowA): Declare.
(CpuUnknownFlags): Update.
* config/tc-i386.c (cpu_sub_arch_name): Declare.
(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
3DNow!. Athlon additionally implies 3DNow!A. Several new
entries (those starting with a dot are for sub-arch specification).
(set_cpu_arch): Handle sub-arch specifications.
(parse_insn): Distinguish between instructions not supported because
of insufficient CPU features and because of 64-bit mode.
* doc/c-i386.texi: Describe enhanced .arch directive.
include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
available only with SSE2. Change the MMX additions introduced by SSE
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
instructions by their now designated identifier (since combining i686
and 3DNow! does not really imply 3DNow!A).
Eric Botcazou
Nick Clifton
Jim Wilson
Alan Modra
Marek Michalkiewicz
Tomer Levi
Ian Lance Taylor
Hans-Peter Nilsson
Joern Rennecke
Richard Sandiford
Jan Beulich
Paul Brook
Ben Elliston
Mark Mitchell
Bob Wilson
Richard Earnshaw
H.J. Lu