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710 Commits

Author SHA1 Message Date
Joern Rennecke
ae51a426eb 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> 
opcodes:
	* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
	nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
	* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
	accordingly.
bfd:
	* archures.c: Add bfd_mach_sh4_nommu_nofpu.
	* cpu-sh.c: Ditto.
	* elf32-sh.c: Ditto.
	* bfd-in2.h: Regenerate.
include/elf:
	* sh.h: Add EF_SH4_NOMMU_NOFPU.
gas:
	* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
	-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
	(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
	the most general type or the user specifically requested it.
	(md_assemble): Add a new error message for when an instruction
	is understood, but is not allowed due to an -isa option.
 2004-03-03 18:01:49 +00:00
Richard Sandiford
676a64f422 Add fr450 support. 2004-03-01 10:11:46 +00:00
Richard Sandiford
c7a48b9ac9 cpu/ 
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
	(scutss): Change unit to I0.
	(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
	(mqsaths): Fix FR400-MAJOR categorization.
	(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
	(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
	* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
	combinations.

opcodes/
	* frv-desc.c, frv-opc.c: Regenerate.

sim/frv/
	* cache.c (frv_cache_init): Change fr400 cache statistics to match
	the fr405.
	(non_cache_access): Add missing breaks.
	* interrupts.c (set_exception_status_registers): Always set EAR15
	for data_access_errors.
	* memory.c (fr400_check_write_address): Remove redundant alignment
	check.
	* model.c: Regenerate.
 2004-03-01 09:42:33 +00:00
Richard Sandiford
8ae0baa268 cpu/ 
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
	(rstb, rsth, rst, rstd, rstq): Delete.
	(rstbf, rsthf, rstf, rstdf, rstqf): Delete.

gas/testsuite/
	* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
	(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
	* gas/frv/allinsn.d: Update accordingly.

opcodes/
	* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.

sim/frv/
	* decode.c, decode.h, model.c, sem.c: Regenerate.

sim/testsuite/
	* sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete.
	* sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete.
 2004-03-01 09:26:33 +00:00
Joern Rennecke
ce11586c0b 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> 
* sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
	Also correct mistake in the comment.
 2004-02-27 14:17:36 +00:00
Joern Rennecke
6a5709a5a1 2004-02-23 Andrew Stubbs <andrew.stubbs@superh.com> 
gas:
	* tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
	nibble types to assembler.
opcodes:
	* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
	ensure that double registers have even numbers.
	Add REG_N_B01 for nn01 (binary 01) nibble to ensure
	that reserved instruction 0xfffd does not decode the same
	as 0xfdfd (ftrv).
	* sh-opc.h: Add REG_N_D nibble type and use it whereever
	REG_N refers to a double register.
	Add REG_N_B01 nibble type and use it instead of REG_NM
	in ftrv.
	Adjust the bit patterns in a few comments.
 2004-02-26 16:14:42 +00:00
Aldy Hernandez
e5d2b64f53 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. 2004-02-26 03:24:44 +00:00
Aldy Hernandez
1f04b05ff5 2004-02-20 Aldy Hernandez <aldyh@redhat.com> 
* ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 2004-02-20 05:10:13 +00:00
Aldy Hernandez
2f3b870051 2004-02-20 Aldy Hernandez <aldyh@redhat.com> 
* ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 2004-02-20 04:56:34 +00:00
Aldy Hernandez
f0b26da617 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, 
mtivor32, mtivor33, mtivor34.
 2004-02-20 04:45:37 +00:00
Aldy Hernandez
23d59c56c9 2004-02-19 Aldy Hernandez <aldyh@redhat.com> 
* ppc-opc.c: Add mfmcar.
 2004-02-20 00:17:23 +00:00
Nick Clifton
34920d91a5 Apply fixes for Maverick Crunch 2004-02-18 16:28:18 +00:00
Ben Elliston
44d8648176 * m32r-dis.c: Regenerate. 2004-02-13 03:21:49 +00:00
Michael Snyder
17707c23a8 2004-01-27 Michael Snyder <msnyder@redhat.com> 
* sh-opc.h (sh_table): "fsrra", not "fssra".
 2004-01-28 00:05:47 +00:00
Nick Clifton
fe3a9bc403 Tighten constaints on a few sparc instructions 2004-01-23 12:08:24 +00:00
Jakub Jelinek
ff24f1246e * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args. 2004-01-18 23:46:32 +00:00
Alan Modra
a02a862a31 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not 
1.  Don't print scale factor on AT&T mode when index missing.
 2004-01-18 23:12:47 +00:00
Alexandre Oliva
d164ea7f0f * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended 
when loaded into XR registers.
 2004-01-16 03:16:00 +00:00
Richard Sandiford
cb10e79a50 cpu/ 
* frv.cpu (UNIT): Add IACC.
	(iacc-multiply-r-r): Use it.
	* frv.opc (fr400_unit_mapping): Add entry for IACC.
	(fr500_unit_mapping, fr550_unit_mapping): Likewise.

opcodes/
	* frv-desc.h: Regenerate.
	* frv-desc.c: Regenerate.
	* frv-opc.c: Regenerate.
 2004-01-14 10:05:00 +00:00
Michael Snyder
f532f3fa70 2004-01-13 Michael Snyder <msnyder@redhat.com> 
* sh-dis.c (print_insn_sh): Allocate 4	bytes for insn.
 2004-01-13 19:56:46 +00:00
Paul Brook
e45d06306f * gas/config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from 
do_vfp_sp_reg2.
	(do_vfp_sp2_from_reg2): New function.
	(insns): Use them.
	(do_vfp_dp_from_reg2): Check return values properly.
	* opcodes/arm-opc.h (arm_opcodes): Move generic mcrr after known
	specific opcodes.
	* gas/testsuite/gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
	* gas/testsuite/gas/arm/arm.exp: Add them.
 2004-01-09 11:53:16 +00:00
Daniel Jacobowitz
3ba7a1aacf * Makefile.am (libopcodes_la_DEPENDENCIES) 
(libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
	comment about the problem.
	* Makefile.in: Regenerate.
 2004-01-07 18:39:40 +00:00
Alexandre Oliva
ba2d3f07f2 2003-12-19 Alexandre Oliva <aoliva@redhat.com> 
* frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
cut&paste errors in shifting/truncating numerical operands.
2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
* frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
(parse_s12): Likewise.
2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
* frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
(parse_uslo16): Likewise.
(parse_uhi16): Parse gothi and gotfuncdeschi.
(parse_d12): Parse got12 and gotfuncdesc12.
(parse_s12): Likewise.
 2004-01-06 19:18:43 +00:00
Nick Clifton
3ab4893121 Catch a bug in the msp430 disassembler where an add instruction was confused 
with an rla instruction.  Add a test for this to the testsuite.
 2004-01-02 17:26:11 +00:00
Alan Modra
c9e214e571 Split ChangeLog files. 2004-01-02 11:16:21 +00:00
Christian Groessler
a0bd404eac * z8k-dis.c (intr_names): Removed. 
(print_intr, print_flags): New functions.
	(unparse_instr): Use new functions.
 2003-12-15 22:01:43 +00:00
Nick Clifton
a711c44f29 Add PIPE_O attribute to "pop" instruction. 2003-12-15 12:19:13 +00:00
Mark Mitchell
1ea5b9f8d1 * arm-opc.h (arm_opcodes): Put V6 instructions before XScale 
instructions.
 2003-12-15 05:01:41 +00:00
Hans-Peter Nilsson
8b1ddfd7d1 * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE, 
SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE
	and SWYM_INSN_BYTE instead of raw numbers.
 2003-12-13 14:56:24 +00:00
Zack Weinberg
1f6c9eb084 opcodes: 
* ppc-opc.c (MO): Make optional.
	(RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
	(tlbwe): Accept for both PPC403 and BOOKE.  Make all operands optional.
gas:
	* tc-ppc.c (md_assemble): Rewrite comment about optional operands
	to indicate that 'all or none' is also handled.  Pluralize a
	word in another comment.
gas/testsuite:
	* gas/ppc/booke.s: Add two more forms of the mbar instruction
	and three forms of the tlbwe instruction.
	* gas/ppc/booke.d: Update to match.
 2003-12-10 22:12:50 +00:00
Mark Mitchell
09d92015d3 * gas/arm/arm.exp: Add archv6 and thumbv6. 
* gas/arm/archv6.d: New file.
	* gas/arm/archv6.s: Likewise.
	* gas/arm/thumbv6.d: Likewise.
	* gas/arm/thumbv6.s: Likewise.

	Add V6 support.
	* config/tc-arm.c (ARM_EXT_V6): New macro.
	(ARM_ARCH_V6): Likewise.
	(SHIFT_IMMEDIATE): Likewise.
	(SHIFT_LSL_OR_ASR_IMMEDIATE): Likewise.
	(SHIFT_ASR_IMMEDIATE): Likewise.
	(SHIFT_LSL_IMMMEDIATE): Likewise.
	(do_cps): New function.
	(do_cpsi): Likewise.
	(do_ldrex): Likewise.
	(do_pkhbt): Likewise.
	(do_pkhtb): Likewise.
	(do_qadd16): Likewise.
	(do_rev): Likewise.
	(do_rfe): Likewise.
	(do_sxtah): Likewise.
	(do_sxth): Likewise.
	(do_setend): Likewise.
	(do_smlad): Likewise.
	(do_smlald): Likewise.
	(do_smmul): Likewise.
	(do_ssat): Likewise.
	(do_usat): Likewise.
	(do_srs): Likewise.
	(do_ssat16): Likewise.
	(do_usat16): Likewise.
	(do_strex): Likewise.
	(do_umaal): Likewise.
	(do_cps_mode): Likewise.
	(do_cps_flags): Likewise.
	(do_endian_specifier): Likewise.
	(do_pkh_core): Likewise.
	(do_sat): Likewise.
	(do_sat16): Likewise.
	(insns): Add V6 instructions.
	(do_t_cps): New function.
	(do_t_cpy): Likewise.
	(do_t_setend): Likewise.
	(THUMB_CPY): New macro.
	(tinsns): Add V6 instructions.
	(decode_shift): Handle V6 restricted-shift options.
	(thumb_mov_compare): Support CPY.
	(arm_cores): Add arm1136js and arm1136jfs.
	(arm_archs): Add armv6.
	(arm_fpus): Add arm1136jfs.
	* doc/c-arm.texi (ARM Options): Mention arm1136js, arm1136jfs, and
	armv6 options.

	* gas/arm/arm.exp: Add archv6 and thumbv6.
	* gas/arm/archv6.d: New file.
	* gas/arm/archv6.s: Likewise.
	* gas/arm/thumbv6.d: Likewise.
	* gas/arm/thumbv6.s: Likewise.

	* arm-dis.c (print_arm_insn): Add 'W' macro.
	* arm-opc.h (arm_opcodes): Add V6 instructions.
	(thumb_opcodes): Likewise.
 2003-12-06 01:25:29 +00:00
Michael Snyder
2469ef8b79 2003-12-02 Alexandre Oliva <aoliva@redhat.com> 
* sh-opc.h: Add support for sh4a and no-fpu variants.
        * sh-dis.c: Ditto.
 2003-12-05 22:16:11 +00:00
Michael Snyder
aeadede63f 2003-12-02 Alexandre Oliva <aoliva@redhat.com> 
* sh-opc.h: Add support for sh4a and no-fpu variants.
	* sh-dis.c: Ditto.
 2003-12-05 02:02:32 +00:00
Alan Modra
8f8077465d * openrisc-asm.c: Regenerate. 
* pj-opc.c: Update copyright date.
 2003-12-04 11:07:22 +00:00
Nick Clifton
8884595866 Add support for the M32R2 processor. 2003-12-03 17:38:48 +00:00
Kazu Hirata
e0ab682bec * alpha-opc.c: Remove ARGSUSED. 
* i370-opc.c: Likewise.
	* ppc-opc.c: Likewise.
 2003-12-03 03:15:14 +00:00
Alan Modra
9fa06c65f0 make "dep-am" 2003-12-02 08:14:35 +00:00
Christian Groessler
c8fd013cc2 * z8k-dis.c: Convert to ISO C90. 
* z8kgen.c: Convert to ISO C90.
	(opt): Move long opcode for "ldb rdb,imm8" after short one, now
	the short one is created when assembling.
	* z8k-opc.h: Regenerate with new z8kgen.c.
 2003-11-28 20:12:17 +00:00
Kazu Hirata
122d081a38 * h8300-dis.c (print_colon_thingie): Remove. 2003-11-19 19:44:58 +00:00
Maciej W. Rozycki
1abe91b1db * config/tc-mips.c (macro): Handle new macros: "lca" and "dlca" 
for loading addresses using CALL relocations.
Don't emit CALL relocations when a base register is used.

* gas/mips/lca-svr4pic.d: New test for the "lca" macro.
* gas/mips/lca-xgot.d: Likewise.
* gas/mips/lca.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.

* opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.

* mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and
"dlca".
 2003-11-18 21:22:57 +00:00
Nick Clifton
22a398e190 Add new field to disassemble_info structure: symbol_is_valid() and use it to 
skip displaying arm elf mapping symbols in disassembly output.
 2003-11-14 15:12:44 +00:00
H.J. Lu
f4fa50da5d 2003-11-05 H.J. Lu <hongjiu.lu@intel.com> 
* m68k-opc.c (m68k_opcodes): Reorder "fmovel".
 2003-11-06 04:32:07 +00:00
Daniel Jacobowitz
8e6446ff53 * arm-dis.c (print_arm_insn): Print "-" after "#". 2003-11-03 14:47:22 +00:00
Nick Clifton
f46a9fbb7a Add second argument to rcpp instruction. 2003-10-30 10:03:03 +00:00
Stephane Carrez
fde8b63277 * m68hc11-dis.c: Convert to ISO C90 prototypes. 2003-10-27 09:26:13 +00:00
Nick Clifton
3e60263266 Add ColfFire v4 support 2003-10-21 13:28:59 +00:00
Michael Snyder
d43ff6d27f 2003-06-03 Michael Snyder <msnyder@redhat.com> 
and Bernd Schmidt   <bernds@redhat.com>
        and Alexandre Oliva <aoliva@redhat.com>

        * disassemble.c (disassembler): Add support for h8300sx.
 2003-10-10 22:13:49 +00:00
Dave Brolley
f7c541f680 2003-10-10 Dave Brolley <brolley@redhat.com> 
* frv-asm.c,frv-desc.c,frv-opc.c: Regenerated.
 2003-10-10 19:30:02 +00:00
Dave Brolley
d576f161dd 2003-10-08 Dave Brolley <brolley@redhat.com> 
* frv-desc.[ch], frv-opc.[ch]: Regenerated.
 2003-10-08 18:26:01 +00:00
Bob Wilson
118fecd307 * xtensa-dis.c (fetch_data): Remove numBytes parameter. 
(print_insn_xtensa): Fix call to fetch_data.
 2003-10-01 00:40:22 +00:00