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Carlo Bramini 69b1ffdb01 sim/aarch64: Fix register ordering bug in blr (PR sim/25318) 
A comment in the implementation of blr says:

  /* The pseudo code in the spec says we update LR before fetching.
     the value from the rn.  */

With 'rn' being the register holding the destination address.

This may have been true at one point, but the ISA manual now clearly
shows the destination register being read before the link register is
written.

This commit updates the implementation of blr to match.

sim/aarch64/ChangeLog:

	PR sim/25318
	* simulator.c (blr): Read destination register before calling
	aarch64_save_LR.

Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064
2020-02-06 22:50:26 +00:00
..
aarch64 sim/aarch64: Fix register ordering bug in blr (PR sim/25318) 2020-02-06 22:50:26 +00:00
arm Fix spelling errors 2020-01-17 12:34:03 -06:00
avr Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
bfin Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
common sim: add some stdlib.h includes 2020-01-19 19:48:16 -05:00
cr16 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
cris Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
d10v Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
erc32 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
frv Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
ft32 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
h8300 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
igen Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
iq2000 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
lm32 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
m32c Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
m32r Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
m68hc11 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
mcore Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
microblaze Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
mips Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
mn10300 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
moxie Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
msp430 MSP430: Fix simulator execution of RRUX instruction 2020-01-22 21:52:29 +00:00
or1k Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
ppc Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
pru Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
rl78 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
rx Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
sh Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
sh64 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
testsuite MSP430: Fix simulator execution of RRUX instruction 2020-01-22 21:52:29 +00:00
v850 Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
.gitignore
ChangeLog Add install-strip to sim/ 2019-12-19 11:28:53 -07:00
configure sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
configure.ac
configure.tgt sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
MAINTAINERS sim: Add PRU simulator port 2019-09-23 22:11:02 +01:00
Makefile.in Update copyright year range in all GDB files. 2020-01-01 10:20:53 +04:00
README-HACKING