123 lines
4.7 KiB
Plaintext
123 lines
4.7 KiB
Plaintext
@c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node M32R-Dependent
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@chapter M32R Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter M32R Dependent Features
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@end ifclear
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@c start-sanitize-m32rx
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@cindex M32R support
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@menu
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* M32R-Opts:: M32R Options
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* M32R-Warnings:: M32R Warnings
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@end menu
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@node M32R-Opts
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@section M32R Options
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@cindex options, M32R
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@cindex M32R options
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The Mitsubishi M32R version of @code{@value{AS}} has a few machine
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dependent options:
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@table @code
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@item --m32rx
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@cindex @samp{--m32rx} option, M32RX
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@cindex architecture options, M32RX
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@cindex M32R architecture options
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@code{@value{AS}} can assemble code for several different members of the
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Mitsubishi M32R family. Normally the default is to assemble code for
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the M32R microprocessor. This option may be used to change the default
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to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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@item --warn-explicit-parallel-conflicts
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@cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} to produce warning messages when
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questionable parallel instructions are encountered. This option is
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enabled by default, but @code{@value{GCC}} disables it when it invokes
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@code{@value{AS}} directly. Questionable instructions are those whoes
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behaviour would be different if they were executed sequentially. For
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example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
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different result from @samp{mv r1, r2 \n mv r3, r1} since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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@item --no-warn-explicit-parallel-conflicts
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@cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} not to produce warning messages when
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questionable parallel instructions are encountered.
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@end table
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@node M32R-Warnings
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@section M32R Warnings
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@cindex warnings, M32R
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@cindex M32R warnings
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There are several warning and error messages that can be produced by
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@code{@value{AS}} which are specific to the M32R:
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@table @code
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@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the left hand instruction is used as an input register in the right hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
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move instruction and the input to the neg instruction.
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@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the right hand instruction is used as an input register in the left hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
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neg instruction and the input to the move instruction.
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@item instruction @samp{...} is for the M32RX only
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This message is produced when the assembler encounters an instruction
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which is only supported by the M32Rx processor, and the @samp{--m32rx}
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command line flag has not been specified to allow assembly of such
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instructions.
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@item only the NOP instruction can be issued in parallel on the m32r
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This message is produced when the assembler encounters a parallel
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instruction which does not involve a NOP instruction and the
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@samp{--m32rx} command line flag has not been specified. Only the M32Rx
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processor is able to execute two instructions in parallel.
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@item instruction @samp{...} cannot be executed in parallel.
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This message is produced when the assembler encounters a parallel
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instruction which is made up of one or two instructions which cannot be
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executed in parallel.
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@item Instructions share the same execution pipeline
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This message is produced when the assembler encounters a parallel
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instruction whoes components both use the same execution pipeline.
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@item Instructions write to the same destination register.
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This message is produced when the assembler encounters a parallel
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instruction where both components attempt to modify the same register.
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For example these code fragments will produce this message:
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@samp{mv r1, r2 || neg r1, r3}
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@samp{jl r0 || mv r14, r1}
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@samp{st r2, @@-r1 || mv r1, r3}
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@samp{mv r1, r2 || ld r0, @@r1+}
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@end table
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@c end-sanitize-m32rx
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