250 lines
11 KiB
C
250 lines
11 KiB
C
/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */
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/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */
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/* OBSOLETE Contributed by Cygnus Support. */
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/* OBSOLETE */
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/* OBSOLETE This file is part of GDB, the GNU debugger. */
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/* OBSOLETE */
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/* OBSOLETE This program is free software; you can redistribute it and/or modify */
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/* OBSOLETE it under the terms of the GNU General Public License as published by */
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/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */
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/* OBSOLETE any later version. */
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/* OBSOLETE */
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/* OBSOLETE This program is distributed in the hope that it will be useful, */
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/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
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/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
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/* OBSOLETE GNU General Public License for more details. */
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/* OBSOLETE */
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/* OBSOLETE You should have received a copy of the GNU General Public License along */
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/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */
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/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE #ifndef _CPU_H_ */
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/* OBSOLETE #define _CPU_H_ */
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/* OBSOLETE */
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/* OBSOLETE enum { */
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/* OBSOLETE NR_GENERAL_PURPOSE_REGISTERS = 64, */
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/* OBSOLETE NR_CONTROL_REGISTERS = 64, */
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/* OBSOLETE NR_ACCUMULATORS = 2, */
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/* OBSOLETE STACK_POINTER_GPR = 63, */
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/* OBSOLETE NR_STACK_POINTERS = 2, */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE enum { */
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/* OBSOLETE processor_status_word_cr = 0, */
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/* OBSOLETE backup_processor_status_word_cr = 1, */
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/* OBSOLETE program_counter_cr = 2, */
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/* OBSOLETE backup_program_counter_cr = 3, */
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/* OBSOLETE debug_backup_processor_status_word_cr = 4, */
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/* OBSOLETE debug_backup_program_counter_cr = 5, */
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/* OBSOLETE reserved_6_cr = 6, */
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/* OBSOLETE repeat_count_cr = 7, */
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/* OBSOLETE repeat_start_address_cr = 8, */
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/* OBSOLETE repeat_end_address_cr = 9, */
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/* OBSOLETE modulo_start_address_cr = 10, */
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/* OBSOLETE modulo_end_address_cr = 11, */
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/* OBSOLETE instruction_break_address_cr = 14, */
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/* OBSOLETE eit_vector_base_cr = 15, */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE */
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/* OBSOLETE enum { */
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/* OBSOLETE PSW_SM = 0, */
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/* OBSOLETE PSW_EA = 2, */
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/* OBSOLETE PSW_DB = 3, */
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/* OBSOLETE PSW_DS = 4, */
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/* OBSOLETE PSW_IE = 5, */
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/* OBSOLETE PSW_RP = 6, */
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/* OBSOLETE PSW_MD = 7, */
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/* OBSOLETE PSW_F0 = 17, */
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/* OBSOLETE PSW_F1 = 19, */
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/* OBSOLETE PSW_F2 = 21, */
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/* OBSOLETE PSW_F3 = 23, */
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/* OBSOLETE PSW_S = 25, */
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/* OBSOLETE PSW_V = 27, */
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/* OBSOLETE PSW_VA = 29, */
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/* OBSOLETE PSW_C = 31, */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE /* aliases for PSW flag numbers (F0..F7) */ */
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/* OBSOLETE enum */
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/* OBSOLETE { */
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/* OBSOLETE PSW_S_FLAG = 4, */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE typedef struct _registers { */
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/* OBSOLETE unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS]; */
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/* OBSOLETE /* keep track of the stack pointer */ */
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/* OBSOLETE unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */ */
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/* OBSOLETE unsigned32 current_sp; */
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/* OBSOLETE unsigned32 control[NR_CONTROL_REGISTERS]; */
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/* OBSOLETE unsigned64 accumulator[NR_ACCUMULATORS]; */
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/* OBSOLETE } registers; */
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/* OBSOLETE */
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/* OBSOLETE typedef enum _cpu_units { */
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/* OBSOLETE memory_unit, */
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/* OBSOLETE integer_unit, */
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/* OBSOLETE any_unit, */
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/* OBSOLETE } cpu_units; */
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/* OBSOLETE */
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/* OBSOLETE /* In order to support parallel instructions, which one instruction can be */
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/* OBSOLETE writing to a register that is used as input to another, queue up the */
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/* OBSOLETE writes to the end of the instruction boundaries. */ */
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/* OBSOLETE */
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/* OBSOLETE #define MAX_WRITE32 16 */
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/* OBSOLETE #define MAX_WRITE64 2 */
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/* OBSOLETE */
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/* OBSOLETE struct _write32 { */
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/* OBSOLETE int num; /* # of 32-bit writes queued up */ */
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/* OBSOLETE unsigned32 value[MAX_WRITE32]; /* value to write */ */
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/* OBSOLETE unsigned32 mask[MAX_WRITE32]; /* mask to use */ */
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/* OBSOLETE unsigned32 *ptr[MAX_WRITE32]; /* address to write to */ */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE struct _write64 { */
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/* OBSOLETE int num; /* # of 64-bit writes queued up */ */
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/* OBSOLETE unsigned64 value[MAX_WRITE64]; /* value to write */ */
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/* OBSOLETE unsigned64 *ptr[MAX_WRITE64]; /* address to write to */ */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE struct _sim_cpu { */
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/* OBSOLETE cpu_units unit; */
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/* OBSOLETE registers regs; */
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/* OBSOLETE sim_cpu_base base; */
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/* OBSOLETE int trace_call_p; /* Whether to do call tracing. */ */
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/* OBSOLETE int trace_trap_p; /* If unknown traps dump out the regs */ */
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/* OBSOLETE int trace_action; /* trace bits at end of instructions */ */
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/* OBSOLETE int left_kills_right_p; /* left insn kills insn in right slot of -> */ */
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/* OBSOLETE int mvtsys_left_p; /* left insn was mvtsys */ */
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/* OBSOLETE int did_trap; /* we did a trap & need to finish it */ */
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/* OBSOLETE struct _write32 write32; /* queued up 32-bit writes */ */
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/* OBSOLETE struct _write64 write64; /* queued up 64-bit writes */ */
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/* OBSOLETE }; */
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/* OBSOLETE */
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/* OBSOLETE #define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr]) */
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/* OBSOLETE #define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr]) */
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/* OBSOLETE #define PSWL (*AL2_4(&PSW)) */
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/* OBSOLETE #define PSWH (*AH2_4(&PSW)) */
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/* OBSOLETE #define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr]) */
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/* OBSOLETE #define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr]) */
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/* OBSOLETE #define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr]) */
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/* OBSOLETE #define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr]) */
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/* OBSOLETE #define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr]) */
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/* OBSOLETE #define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr]) */
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/* OBSOLETE #define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr]) */
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/* OBSOLETE #define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr]) */
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/* OBSOLETE #define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr]) */
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/* OBSOLETE #define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr]) */
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/* OBSOLETE #define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr]) */
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/* OBSOLETE #define GPR (STATE_CPU (sd, 0)->regs.general_purpose) */
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/* OBSOLETE #define GPR_CLEAR(N) (GPR[(N)] = 0) */
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/* OBSOLETE #define ACC (STATE_CPU (sd, 0)->regs.accumulator) */
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/* OBSOLETE #define CREG (STATE_CPU (sd, 0)->regs.control) */
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/* OBSOLETE #define SP (GPR[STACK_POINTER_GPR]) */
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/* OBSOLETE #define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p) */
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/* OBSOLETE #define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p) */
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/* OBSOLETE #define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action) */
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/* OBSOLETE #define TRACE_ACTION_CALL 0x00000001 /* call occurred */ */
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/* OBSOLETE #define TRACE_ACTION_RETURN 0x00000002 /* return occurred */ */
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/* OBSOLETE */
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/* OBSOLETE #define WRITE32 (STATE_CPU (sd, 0)->write32) */
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/* OBSOLETE #define WRITE32_NUM (WRITE32.num) */
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/* OBSOLETE #define WRITE32_PTR(N) (WRITE32.ptr[N]) */
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/* OBSOLETE #define WRITE32_MASK(N) (WRITE32.mask[N]) */
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/* OBSOLETE #define WRITE32_VALUE(N) (WRITE32.value[N]) */
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/* OBSOLETE #define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff) */
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/* OBSOLETE */
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/* OBSOLETE #define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \ */
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/* OBSOLETE do { \ */
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/* OBSOLETE int _num = WRITE32_NUM; \ */
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/* OBSOLETE if (_num >= MAX_WRITE32) \ */
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/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
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/* OBSOLETE "Too many queued 32-bit writes"); \ */
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/* OBSOLETE WRITE32_PTR(_num) = PTR; \ */
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/* OBSOLETE WRITE32_VALUE(_num) = VALUE; \ */
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/* OBSOLETE WRITE32_MASK(_num) = MASK; \ */
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/* OBSOLETE WRITE32_NUM = _num+1; \ */
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/* OBSOLETE } while (0) */
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/* OBSOLETE */
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/* OBSOLETE #define DID_TRAP (STATE_CPU (sd, 0)->did_trap) */
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/* OBSOLETE */
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/* OBSOLETE #define WRITE64 (STATE_CPU (sd, 0)->write64) */
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/* OBSOLETE #define WRITE64_NUM (WRITE64.num) */
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/* OBSOLETE #define WRITE64_PTR(N) (WRITE64.ptr[N]) */
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/* OBSOLETE #define WRITE64_VALUE(N) (WRITE64.value[N]) */
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/* OBSOLETE #define WRITE64_QUEUE(PTR, VALUE) \ */
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/* OBSOLETE do { \ */
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/* OBSOLETE int _num = WRITE64_NUM; \ */
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/* OBSOLETE if (_num >= MAX_WRITE64) \ */
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/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
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/* OBSOLETE "Too many queued 64-bit writes"); \ */
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/* OBSOLETE WRITE64_PTR(_num) = PTR; \ */
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/* OBSOLETE WRITE64_VALUE(_num) = VALUE; \ */
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/* OBSOLETE WRITE64_NUM = _num+1; \ */
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/* OBSOLETE } while (0) */
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/* OBSOLETE */
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/* OBSOLETE #define DPSW_VALID 0xbf005555 */
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/* OBSOLETE #define PSW_VALID 0xb7005555 */
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/* OBSOLETE #define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */ */
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/* OBSOLETE #define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */ */
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/* OBSOLETE */
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/* OBSOLETE /* Verify that the instruction is in the correct slot */ */
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/* OBSOLETE */
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/* OBSOLETE #define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX) */
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/* OBSOLETE extern int is_wrong_slot */
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/* OBSOLETE (SIM_DESC sd, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE itable_index index); */
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/* OBSOLETE */
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/* OBSOLETE #define IS_CONDITION_OK is_condition_ok(sd, cia, CCC) */
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/* OBSOLETE extern int is_condition_ok */
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/* OBSOLETE (SIM_DESC sd, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE int cond); */
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/* OBSOLETE */
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/* OBSOLETE #define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */ */
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/* OBSOLETE */
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/* OBSOLETE /* Internal breakpoint instruction is syscall 5 */ */
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/* OBSOLETE #define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05} */
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/* OBSOLETE #define SIM_BREAKPOINT_SIZE (4) */
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/* OBSOLETE */
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/* OBSOLETE /* Call occurred */ */
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/* OBSOLETE extern void call_occurred */
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/* OBSOLETE (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE address_word nia); */
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/* OBSOLETE */
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/* OBSOLETE /* Return occurred */ */
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/* OBSOLETE extern void return_occurred */
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/* OBSOLETE (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia, */
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/* OBSOLETE address_word nia); */
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/* OBSOLETE */
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/* OBSOLETE /* Whether to do call tracing. */ */
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/* OBSOLETE extern int d30v_call_trace_p; */
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/* OBSOLETE */
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/* OBSOLETE /* Read/write functions for system call interface. */ */
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/* OBSOLETE extern int d30v_read_mem */
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/* OBSOLETE (host_callback *cb, */
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/* OBSOLETE struct cb_syscall *sc, */
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/* OBSOLETE unsigned long taddr, */
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/* OBSOLETE char *buf, */
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/* OBSOLETE int bytes); */
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/* OBSOLETE */
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/* OBSOLETE extern int d30v_write_mem */
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/* OBSOLETE (host_callback *cb, */
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/* OBSOLETE struct cb_syscall *sc, */
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/* OBSOLETE unsigned long taddr, */
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/* OBSOLETE const char *buf, */
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/* OBSOLETE int bytes); */
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/* OBSOLETE */
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/* OBSOLETE /* Process all of the queued up writes in order now */ */
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/* OBSOLETE void unqueue_writes */
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/* OBSOLETE (SIM_DESC sd, */
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/* OBSOLETE sim_cpu *cpu, */
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/* OBSOLETE address_word cia); */
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/* OBSOLETE */
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/* OBSOLETE #endif /* _CPU_H_ */ */
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