7433498b7f
This patch fixes a number of bugs in ppc32 plt stub matching code. 1) The 4-insn stubs for shared libs and PIEs weren't matched. 2) The executable stub miscalculated PLT entry address (by oring a sign-extended quantity rather than adding). 3) Comments were not accurate. In addition, the insn arrays are made const. * ppc-linux-tdep.c (powerpc32_plt_stub): Make const. (powerpc32_plt_stub_so_1): Rename from powerpc32_plt_stub_so. Remove nop. Make const. Comment. (powerpc32_plt_stub_so_2): New. (POWERPC32_PLT_CHECK_LEN): Rename from POWERPC32_PLT_STUB_LEN. Correct count. Update uses. (ppc_skip_trampoline_code): Match powerpc32_plt_stub_so_2 too. Move common code reading PLT entry word. Correct powerpc32_plt_stub PLT address calculation. * ppc64-tdep.c (ppc64_standard_linkage1): Make const. (ppc64_standard_linkage2, ppc64_standard_linkage3): Likewise. (ppc64_standard_linkage4, ppc64_standard_linkage5): Likewise. (ppc64_standard_linkage6, ppc64_standard_linkage7): Likewise. (ppc64_standard_linkage8): Likewise. * rs6000-tdep.c (ppc_insns_match_pattern): Make pattern const. Correct insns description. * ppc-tdep.h (ppc_insns_match_pattern): Update prototype. Reviewed-By: Yao Qi <qiyaoltc@gmail.com>
349 lines
12 KiB
C++
349 lines
12 KiB
C++
/* Target-dependent code for GDB, the GNU debugger.
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Copyright (C) 2000-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef PPC_TDEP_H
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#define PPC_TDEP_H
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struct gdbarch;
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struct frame_info;
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struct value;
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struct regcache;
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struct type;
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/* From ppc-sysv-tdep.c ... */
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enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
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struct value *function,
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struct type *valtype,
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struct regcache *regcache,
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gdb_byte *readbuf,
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const gdb_byte *writebuf);
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enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
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struct value *function,
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struct type *valtype,
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struct regcache *regcache,
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gdb_byte *readbuf,
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const gdb_byte *writebuf);
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CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
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struct value *function,
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struct regcache *regcache,
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CORE_ADDR bp_addr, int nargs,
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struct value **args, CORE_ADDR sp,
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int struct_return,
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CORE_ADDR struct_addr);
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CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
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struct value *function,
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struct regcache *regcache,
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CORE_ADDR bp_addr, int nargs,
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struct value **args, CORE_ADDR sp,
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int struct_return,
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CORE_ADDR struct_addr);
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enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
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struct value *function,
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struct type *valtype,
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struct regcache *regcache,
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gdb_byte *readbuf,
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const gdb_byte *writebuf);
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/* From rs6000-tdep.c... */
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int altivec_register_p (struct gdbarch *gdbarch, int regno);
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int vsx_register_p (struct gdbarch *gdbarch, int regno);
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int spe_register_p (struct gdbarch *gdbarch, int regno);
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/* Return non-zero if the architecture described by GDBARCH has
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floating-point registers (f0 --- f31 and fpscr). */
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int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
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/* Return non-zero if the architecture described by GDBARCH has
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Altivec registers (vr0 --- vr31, vrsave and vscr). */
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int ppc_altivec_support_p (struct gdbarch *gdbarch);
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/* Return non-zero if the architecture described by GDBARCH has
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VSX registers (vsr0 --- vsr63). */
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int vsx_support_p (struct gdbarch *gdbarch);
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std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
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(struct regcache *regcache);
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/* Register set description. */
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struct ppc_reg_offsets
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{
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/* General-purpose registers. */
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int r0_offset;
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int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
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int xr_size; /* size for cr, xer, mq. */
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int pc_offset;
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int ps_offset;
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int cr_offset;
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int lr_offset;
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int ctr_offset;
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int xer_offset;
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int mq_offset;
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/* Floating-point registers. */
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int f0_offset;
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int fpscr_offset;
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int fpscr_size;
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/* AltiVec registers. */
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int vr0_offset;
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int vscr_offset;
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int vrsave_offset;
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};
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extern void ppc_supply_reg (struct regcache *regcache, int regnum,
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const gdb_byte *regs, size_t offset, int regsize);
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extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
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gdb_byte *regs, size_t offset, int regsize);
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/* Supply register REGNUM in the general-purpose register set REGSET
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from the buffer specified by GREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_gregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *gregs, size_t len);
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/* Supply register REGNUM in the floating-point register set REGSET
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from the buffer specified by FPREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_fpregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *fpregs, size_t len);
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/* Supply register REGNUM in the Altivec register set REGSET
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from the buffer specified by VRREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_vrregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *vrregs, size_t len);
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/* Supply register REGNUM in the VSX register set REGSET
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from the buffer specified by VSXREGS and LEN to register cache
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REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
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extern void ppc_supply_vsxregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *vsxregs, size_t len);
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/* Collect register REGNUM in the general-purpose register set
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REGSET, from register cache REGCACHE into the buffer specified by
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GREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_gregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *gregs, size_t len);
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/* Collect register REGNUM in the floating-point register set
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REGSET, from register cache REGCACHE into the buffer specified by
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FPREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_fpregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *fpregs, size_t len);
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/* Collect register REGNUM in the Altivec register set
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REGSET from register cache REGCACHE into the buffer specified by
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VRREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_vrregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *vrregs, size_t len);
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/* Collect register REGNUM in the VSX register set
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REGSET from register cache REGCACHE into the buffer specified by
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VSXREGS and LEN. If REGNUM is -1, do this for all registers in
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REGSET. */
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extern void ppc_collect_vsxregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *vsxregs, size_t len);
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/* Private data that this module attaches to struct gdbarch. */
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/* ELF ABI version used by the inferior. */
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enum powerpc_elf_abi
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{
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POWERPC_ELF_AUTO,
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POWERPC_ELF_V1,
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POWERPC_ELF_V2,
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POWERPC_ELF_LAST
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};
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/* Vector ABI used by the inferior. */
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enum powerpc_vector_abi
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{
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POWERPC_VEC_AUTO,
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POWERPC_VEC_GENERIC,
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POWERPC_VEC_ALTIVEC,
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POWERPC_VEC_SPE,
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POWERPC_VEC_LAST
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};
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/* long double ABI version used by the inferior. */
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enum powerpc_long_double_abi
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{
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POWERPC_LONG_DOUBLE_AUTO,
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POWERPC_LONG_DOUBLE_IBM128,
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POWERPC_LONG_DOUBLE_IEEE128,
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POWERPC_LONG_DOUBLE_LAST
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};
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struct gdbarch_tdep
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{
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int wordsize; /* Size in bytes of fixed-point word. */
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int soft_float; /* Avoid FP registers for arguments? */
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enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
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/* Format to use for the "long double" data type. */
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enum powerpc_long_double_abi long_double_abi;
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/* How to pass vector arguments. Never set to AUTO or LAST. */
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enum powerpc_vector_abi vector_abi;
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int ppc_gp0_regnum; /* GPR register 0 */
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int ppc_toc_regnum; /* TOC register */
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int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
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int ppc_cr_regnum; /* Condition register */
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int ppc_lr_regnum; /* Link register */
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int ppc_ctr_regnum; /* Count register */
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int ppc_xer_regnum; /* Integer exception register */
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/* Not all PPC and RS6000 variants will have the registers
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represented below. A -1 is used to indicate that the register
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is not present in this variant. */
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/* Floating-point registers. */
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int ppc_fp0_regnum; /* Floating-point register 0. */
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int ppc_fpscr_regnum; /* fp status and condition register. */
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/* Multiplier-Quotient Register (older POWER architectures only). */
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int ppc_mq_regnum;
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/* POWER7 VSX registers. */
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int ppc_vsr0_regnum; /* First VSX register. */
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int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
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int ppc_efpr0_regnum; /* First Extended FP register. */
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/* Altivec registers. */
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int ppc_vr0_regnum; /* First AltiVec register. */
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int ppc_vrsave_regnum; /* Last AltiVec register. */
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/* SPE registers. */
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int ppc_ev0_upper_regnum; /* First GPR upper half register. */
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int ppc_ev0_regnum; /* First ev register. */
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int ppc_acc_regnum; /* SPE 'acc' register. */
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int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
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/* Decimal 128 registers. */
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int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
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/* Offset to ABI specific location where link register is saved. */
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int lr_frame_offset;
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/* An array of integers, such that sim_regno[I] is the simulator
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register number for GDB register number I, or -1 if the
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simulator does not implement that register. */
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int *sim_regno;
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/* ISA-specific types. */
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struct type *ppc_builtin_type_vec64;
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struct type *ppc_builtin_type_vec128;
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int (*ppc_syscall_record) (struct regcache *regcache);
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};
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/* Constants for register set sizes. */
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enum
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{
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ppc_num_gprs = 32, /* 32 general-purpose registers. */
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ppc_num_fprs = 32, /* 32 floating-point registers. */
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ppc_num_srs = 16, /* 16 segment registers. */
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ppc_num_vrs = 32, /* 32 Altivec vector registers. */
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ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
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ppc_num_vsrs = 64, /* 64 VSX vector registers. */
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ppc_num_efprs = 32 /* 32 Extended FP registers. */
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};
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/* Register number constants. These are GDB internal register
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numbers; they are not used for the simulator or remote targets.
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Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
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numbers above PPC_NUM_REGS. So are segment registers and other
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target-defined registers. */
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enum {
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PPC_R0_REGNUM = 0,
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PPC_F0_REGNUM = 32,
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PPC_PC_REGNUM = 64,
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PPC_MSR_REGNUM = 65,
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PPC_CR_REGNUM = 66,
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PPC_LR_REGNUM = 67,
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PPC_CTR_REGNUM = 68,
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PPC_XER_REGNUM = 69,
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PPC_FPSCR_REGNUM = 70,
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PPC_MQ_REGNUM = 71,
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PPC_SPE_UPPER_GP0_REGNUM = 72,
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PPC_SPE_ACC_REGNUM = 104,
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PPC_SPE_FSCR_REGNUM = 105,
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PPC_VR0_REGNUM = 106,
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PPC_VSCR_REGNUM = 138,
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PPC_VRSAVE_REGNUM = 139,
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PPC_VSR0_UPPER_REGNUM = 140,
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PPC_VSR31_UPPER_REGNUM = 171,
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PPC_NUM_REGS
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};
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/* Big enough to hold the size of the largest register in bytes. */
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#define PPC_MAX_REGISTER_SIZE 64
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/* An instruction to match. */
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struct ppc_insn_pattern
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{
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unsigned int mask; /* mask the insn with this... */
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unsigned int data; /* ...and see if it matches this. */
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int optional; /* If non-zero, this insn may be absent. */
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};
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extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
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const struct ppc_insn_pattern *pattern,
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unsigned int *insns);
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extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
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extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
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extern int ppc_process_record (struct gdbarch *gdbarch,
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struct regcache *regcache, CORE_ADDR addr);
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/* Instruction size. */
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#define PPC_INSN_SIZE 4
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/* Estimate for the maximum number of instrctions in a function epilogue. */
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#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
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#endif /* ppc-tdep.h */
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