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Nick Clifton 5ab6d79e70 More AArch64 simulator improvements. 
* cpustate.c (aarch64_get_FP_half): New function.  Read a vector
	register as a half precision floating point number.
	(aarch64_set_FP_half): New function.  Similar, but for setting
	a half precision register.
	(aarch64_get_thread_id): New function.  Returns the value of the
	CPU's TPIDR register.
	(aarch64_get_FPCR): New function.  Returns the value of the CPU's
	floating point control register.
	(aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
	register.
	* cpustate.h: Add prototypes for new functions.
	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	* memory.c: Use unaligned core access functions for all memory
	reads and writes.
	* simulator.c (HALT_NYI): Generate an error message if tracing
	will not tell the user why the simulator is halting.
	(HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
	(INSTR): New time-saver macro.
	(fldrb_abs): New function.  Loads an 8-bit value using a scaled
	offset.
	(fldrh_abs): New function.  Likewise for 16-bit values.
	(do_vec_SSHL): Allow for negative shift values.
	(do_vec_USHL): Likewise.
	(do_vec_SHL): Correct computation of shift amount.
	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	shifts and computation of shift value.
	(clz): New function.  Counts leading zero bits.
	(do_vec_CLZ): New function.  Implements CLZ (vector).
	(do_vec_MOV_element): Call do_vec_CLZ.
	(dexSimpleFPCondCompare): Implement.
	(do_FCVT_half_to_single): New function.  Implements one of the
	FCVT operations.
	(do_FCVT_half_to_double): New function.  Likewise.
	(do_FCVT_single_to_half): New function.  Likewise.
	(do_FCVT_double_to_half): New function.  Likewise.
	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	(do_scalar_SHL): Handle negative shifts.
	(do_scalar_shift): Handle SSHR.
	(do_scalar_USHL): New function.
	(do_double_add): Simplify to just performing a double precision
	add operation.  Move remaining code into...
	(do_scalar_vec): ... New function.
	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	functions.
	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	registers.
	(system_set): New function.
	(do_MSR_immediate): New function.  Stub for now.
	(do_MSR_reg): New function.  Likewise. Partially implements MSR
	instruction.
	(do_SYS): New function.  Stub for now,
	(dexSystem): Call new functions.
 		2016-03-23 17:37:30 +00:00
..
ChangeLog More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
Makefile.in GDB copyright headers update after running GDB's copyright.py script. 2016-01-01 08:43:22 +04:00
aclocal.m4
…
config.in sim: move many common settings from CPPFLAGS to config.h 2016-01-10 18:54:41 -05:00
configure sim: move many common settings from CPPFLAGS to config.h 2016-01-10 18:54:41 -05:00
configure.ac sim: allow the environment configure option everywhere 2016-01-10 17:03:36 -05:00
cpustate.c More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
cpustate.h More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
decode.h GDB copyright headers update after running GDB's copyright.py script. 2016-01-01 08:43:22 +04:00
interp.c sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly 2016-01-06 21:48:59 -05:00
memory.c More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
memory.h Add simulation of MUL and NEG instructions to AArch64 simulator. 2016-03-18 09:32:32 +00:00
sim-main.h More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
simulator.c More AArch64 simulator improvements. 2016-03-23 17:37:30 +00:00
simulator.h sim: aarch64: switch to common disassembler tracing 2016-01-05 14:37:46 -05:00