36dbc8bb7c
* cgen-mem.h: Delete inclusion of sim-xcat.h. * cgen-sim.h: Ditto. * sim-alu.h: Replace sim-xcat.h with symcat.h. * sim-n-bits.h: Ditto. * sim-n-core.h: Ditto. * sim-n-endian.h: Ditto.
311 lines
9.1 KiB
C
311 lines
9.1 KiB
C
/* Simulator header for Cpu tools GENerated simulators.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef CGEN_SIM_H
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#define CGEN_SIM_H
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#define PC CPU (h_pc)
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/* Instruction field support macros. */
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#define EXTRACT_SIGNED(val, total, start, length) \
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(((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \
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^ (1 << ((length) - 1))) \
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- (1 << ((length) - 1)))
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#define EXTRACT_UNSIGNED(val, total, start, length) \
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(((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1))
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/* Compute number of longs required to hold N bits. */
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#define HOST_LONGS_FOR_BITS(n) \
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(((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
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/* Execution support. */
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/* Forward decls. Defined in the machine generated arch.h and cpu.h files. */
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typedef struct argbuf ARGBUF;
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typedef struct scache SCACHE;
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typedef struct parexec PAREXEC;
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#ifdef SCACHE_P
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/* instruction address */
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typedef PCADDR IADDR;
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/* current instruction address */
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef SCACHE *SEM_ARG;
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#else /* ! SCACHE_P */
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/* instruction address */
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typedef PCADDR IADDR;
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/* current instruction address */
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typedef PCADDR CIA;
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/* argument to semantic functions */
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typedef ARGBUF *SEM_ARG;
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#endif /* ! SCACHE_P */
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/* Semantic functions come in two versions on two axis:
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fast and full (featured), and using or not using scache.
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A full featured simulator is always provided. --enable-sim-fast includes
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support for fast execution by duplicating the semantic code but leaving
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out all features like tracing and profiling.
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Using the scache is selected with --enable-sim-scache. */
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/* FIXME: --enable-sim-fast not implemented yet. */
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/* Types of the machine generated extract and semantic fns. */
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/* FIXME: Eventually conditionalize EXTRACT_FN on WITH_SCACHE. */
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typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
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#if WITH_SCACHE
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#ifdef HAVE_PARALLEL_EXEC
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *, PAREXEC *);
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#else
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *);
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#endif
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#else /* ! WITH_SCACHE */
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#ifdef HAVE_PARALLEL_EXEC
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *, PAREXEC *);
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#else
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typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
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#endif
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#endif
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/* DECODE struct, there is one per instruction. */
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typedef struct {
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/* Using cgen_insn_type requires <cpu>-opc.h. */
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int /*enum cgen_insn_type*/ insn_type;
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const struct cgen_insn *opcode;
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EXTRACT_FN *extract;
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#ifdef HAVE_PARALLEL_EXEC
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#ifdef __GNUC__
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void *read;
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#else
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int read;
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#endif
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#endif
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SEMANTIC_FN *semantic;
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SEMANTIC_FN *semantic_fast;
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#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
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/* Set at runtime. */
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void *sem_full_lab;
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#endif
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#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
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/* Set at runtime. */
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void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */
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#endif
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} DECODE;
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/* Scache data for each cpu. */
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typedef struct cpu_scache {
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/* Simulator cache size. */
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int size;
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#define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size)
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/* Cache. */
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SCACHE *cache;
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#define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache)
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#if 0 /* FIXME: wip */
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/* Free list. */
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SCACHE *free;
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#define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free)
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/* Hash table. */
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SCACHE **hash_table;
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#define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table)
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#endif
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#if WITH_PROFILE_SCACHE_P
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/* Cache hits, misses. */
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unsigned long hits, misses;
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#define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits)
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#define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses)
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#endif
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} CPU_SCACHE;
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/* Default number of cached blocks. */
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#ifdef CONFIG_SIM_CACHE_SIZE
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#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
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#else
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#define SCACHE_DEFAULT_CACHE_SIZE 1024
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#endif
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/* Hash a PC value. */
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/* FIXME: cpu specific */
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#define SCACHE_HASH_PC(state, pc) \
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(((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1))
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/* Non-zero if cache is in use. */
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#define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0)
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/* Install the simulator cache into the simulator. */
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MODULE_INSTALL_FN scache_install;
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/* Flush all cpu's caches. */
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void scache_flush (SIM_DESC);
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/* Scache profiling support. */
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/* Print summary scache usage information. */
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void scache_print_profile (SIM_CPU *cpu, int verbose);
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#if WITH_PROFILE_SCACHE_P
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#define PROFILE_COUNT_SCACHE_HIT(cpu) \
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do { \
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if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
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++ CPU_SCACHE_HITS (cpu); \
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} while (0)
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#define PROFILE_COUNT_SCACHE_MISS(cpu) \
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do { \
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if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
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++ CPU_SCACHE_MISSES (cpu); \
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} while (0)
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#else
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#define PROFILE_COUNT_SCACHE_HIT(cpu)
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#define PROFILE_COUNT_SCACHE_MISS(cpu)
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#endif
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/* Engine support. */
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/* Values to denote parallel/sequential execution. */
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#define EXEC_SEQUENCE 0
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#define EXEC_PARALLEL 1
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/* These are used so that we can compile two copies of the semantic code,
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one with full feature support and one without. */
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/* FIXME: Eventually delete extraction if not using scache. */
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#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
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#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
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#ifdef SCACHE_P
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#define CIA_ADDR(cia) (cia)
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/* extract.c support */
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/* scache_unset is a cache entry that is never used.
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It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
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newval.cache == NULL. */
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extern struct scache scache_unset;
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#define RECORD_IADDR(fld, val) \
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do { (fld) = (val); } while (0)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
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#define SEM_INSN(sem_arg) shouldnt_be_used
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#define SEM_NEXT_PC(sc) ((sc) -> next)
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#define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
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/* Return address a branch insn will branch to.
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This is only used during tracing. */
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#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
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#else /* ! SCACHE_P */
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#define CIA_ADDR(cia) (cia)
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/* extract.c support */
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#define RECORD_IADDR(fld, val) \
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do { (fld) = (val); } while (0)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (sem_arg)
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#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
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#define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length)
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#define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
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#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
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#endif /* ! SCACHE_P */
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/* GNU C's "computed goto" facility is used to speed things up where
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possible. These macros provide a portable way to use them.
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Nesting of these switch statements is done by providing an extra argument
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that distinguishes them. `N' can be a number or symbol.
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Variable `labels_##N' must be initialized with the labels of each case. */
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#ifdef __GNUC__
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#define SWITCH(N, X) goto *X;
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#define CASE(N, X) case_##N##_##X
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#define BREAK(N) goto end_switch_##N
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#define DEFAULT(N) default_##N
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#define ENDSWITCH(N) end_switch_##N:
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#else
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#define SWITCH(N, X) switch (X)
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#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
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#define BREAK(N) break
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#define DEFAULT(N) default
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#define ENDSWITCH(N)
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#endif
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/* Engine control (FIXME). */
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int engine_stop (SIM_DESC);
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void engine_run (SIM_DESC, int, int);
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/*void engine_resume (SIM_DESC, int, int);*/
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/* Simulator state. */
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/* Records simulator descriptor so utilities like @cpu@_dump_regs can be
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called from gdb. */
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extern SIM_DESC current_state;
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/* Simulator state. */
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/* CGEN_STATE contains additional state information not present in
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sim_state_base. */
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typedef struct cgen_state {
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/* FIXME: Moved to sim_state_base. */
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/* argv, env */
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char **argv;
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#define STATE_ARGV(s) ((s) -> cgen_state.argv)
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/* FIXME: Move to sim_state_base. */
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char **envp;
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#define STATE_ENVP(s) ((s) -> cgen_state.envp)
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/* Non-zero if no tracing or profiling is selected. */
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int run_fast_p;
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#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
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} CGEN_STATE;
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/* Additional non-machine generated per-cpu data to go in SIM_CPU.
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The member's name must be `cgen_cpu'. */
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typedef struct {
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/* Simulator's execution cache. */
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#if WITH_SCACHE
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CPU_SCACHE scache;
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#endif /* WITH_SCACHE */
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/* Allow slop in size calcs for case where multiple cpu types are supported
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and space for the specified cpu is malloc'd at run time. */
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double slop;
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} CGEN_CPU;
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/* Various utilities. */
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/* Called after sim_post_argv_init to do any cgen initialization. */
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void cgen_init (SIM_DESC);
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void
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sim_disassemble_insn (SIM_CPU *, const struct cgen_insn *,
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const struct argbuf *, PCADDR, char *);
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#endif /* CGEN_SIM_H */
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