ba46ddd0cf
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (Infinity): Remove.
* sim-main.h (Infinity): Likewise.
* cp1.c (fp_unary, fp_binary): New functions.
(fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
(fp_sqrt): New functions, implemented in terms of the above.
(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
(Recip, SquareRoot): Remove (replaced by functions above).
* sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
(fp_recip, fp_sqrt): New prototypes.
(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
(Recip, SquareRoot): Replace prototypes with #defines which
invoke the functions above.
747 lines
15 KiB
C
747 lines
15 KiB
C
/*> cp1.c <*/
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/* Floating Point Support for gdb MIPS simulators
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This file is part of the MIPS sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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(Originally, this code was in interp.c)
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*/
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#include "sim-main.h"
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#include "sim-fpu.h"
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/* Within cp1.c we refer to sim_cpu directly. */
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#define CPU cpu
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#define SD CPU_STATE(cpu)
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/*-- FPU support routines ---------------------------------------------------*/
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/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
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formats conform to ANSI/IEEE Std 754-1985.
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SINGLE precision floating:
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seeeeeeeefffffffffffffffffffffff
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s = 1bit = sign
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e = 8bits = exponent
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f = 23bits = fraction
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SINGLE precision fixed:
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siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
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s = 1bit = sign
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i = 31bits = integer
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DOUBLE precision floating:
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seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
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s = 1bit = sign
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e = 11bits = exponent
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f = 52bits = fraction
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DOUBLE precision fixed:
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siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
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s = 1bit = sign
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i = 63bits = integer
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*/
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/* Explicit QNaN values used when value required: */
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#define FPQNaN_SINGLE (0x7FBFFFFF)
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#define FPQNaN_WORD (0x7FFFFFFF)
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#define FPQNaN_DOUBLE (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
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#define FPQNaN_LONG (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
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static const char *fpu_format_name (FP_formats fmt);
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#ifdef DEBUG
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static const char *fpu_rounding_mode_name (int rm);
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#endif
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uword64
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value_fpr (sim_cpu *cpu,
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address_word cia,
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int fpr,
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FP_formats fmt)
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{
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uword64 value = 0;
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int err = 0;
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/* Treat unused register values, as fixed-point 64bit values: */
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if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
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{
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#if 1
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/* If request to read data as "uninterpreted", then use the current
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encoding: */
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fmt = FPR_STATE[fpr];
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#else
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fmt = fmt_long;
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#endif
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}
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/* For values not yet accessed, set to the desired format: */
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if (FPR_STATE[fpr] == fmt_uninterpreted)
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{
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FPR_STATE[fpr] = fmt;
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#ifdef DEBUG
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printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
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fpu_format_name (fmt));
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#endif /* DEBUG */
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}
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if (fmt != FPR_STATE[fpr])
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{
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sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
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fpr, fpu_format_name (FPR_STATE[fpr]),
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fpu_format_name (fmt), pr_addr (cia));
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FPR_STATE[fpr] = fmt_unknown;
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}
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if (FPR_STATE[fpr] == fmt_unknown)
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{
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/* Set QNaN value: */
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switch (fmt)
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{
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case fmt_single:
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value = FPQNaN_SINGLE;
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break;
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case fmt_double:
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value = FPQNaN_DOUBLE;
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break;
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case fmt_word:
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value = FPQNaN_WORD;
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break;
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case fmt_long:
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value = FPQNaN_LONG;
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break;
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default:
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err = -1;
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break;
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}
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}
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else if (SizeFGR () == 64)
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{
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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break;
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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value = FGR[fpr];
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break;
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default:
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err = -1;
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break;
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}
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}
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else
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{
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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break;
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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if ((fpr & 1) == 0)
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{
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/* even registers only */
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#ifdef DEBUG
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printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
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fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
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fpr, pr_uword64 ((uword64) FGR[fpr]));
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#endif
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value = ((((uword64) FGR[fpr+1]) << 32)
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| (FGR[fpr] & 0xFFFFFFFF));
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}
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else
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{
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SignalException (ReservedInstruction, 0);
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}
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break;
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default:
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err = -1;
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break;
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}
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}
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if (err)
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SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
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#ifdef DEBUG
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printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
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fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
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SizeFGR ());
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#endif /* DEBUG */
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return (value);
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}
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void
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store_fpr (sim_cpu *cpu,
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address_word cia,
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int fpr,
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FP_formats fmt,
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uword64 value)
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{
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int err = 0;
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#ifdef DEBUG
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printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
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fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
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SizeFGR ());
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#endif /* DEBUG */
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if (SizeFGR () == 64)
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single:
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case fmt_word:
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if (STATE_VERBOSE_P (SD))
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sim_io_eprintf (SD,
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"Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
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pr_addr (cia));
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FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
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FPR_STATE[fpr] = fmt;
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break;
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case fmt_uninterpreted_64:
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fmt = fmt_uninterpreted;
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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FGR[fpr] = value;
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FPR_STATE[fpr] = fmt;
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break;
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default:
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FPR_STATE[fpr] = fmt_unknown;
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err = -1;
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break;
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}
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}
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else
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single:
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case fmt_word:
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FGR[fpr] = (value & 0xFFFFFFFF);
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FPR_STATE[fpr] = fmt;
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break;
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case fmt_uninterpreted_64:
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fmt = fmt_uninterpreted;
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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if ((fpr & 1) == 0)
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{
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/* even register number only */
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FGR[fpr+1] = (value >> 32);
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FGR[fpr] = (value & 0xFFFFFFFF);
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FPR_STATE[fpr + 1] = fmt;
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FPR_STATE[fpr] = fmt;
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}
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else
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{
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FPR_STATE[fpr] = fmt_unknown;
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FPR_STATE[fpr + 1] = fmt_unknown;
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SignalException (ReservedInstruction, 0);
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}
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break;
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default:
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FPR_STATE[fpr] = fmt_unknown;
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err = -1;
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break;
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}
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}
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if (err)
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SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
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#ifdef DEBUG
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printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
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fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt));
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#endif /* DEBUG */
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return;
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}
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int
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NaN (op, fmt)
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uword64 op;
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FP_formats fmt;
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{
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int boolean = 0;
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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{
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sim_fpu wop;
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sim_fpu_32to (&wop, op);
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boolean = sim_fpu_is_nan (&wop);
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break;
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}
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case fmt_double:
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case fmt_long:
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{
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sim_fpu wop;
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sim_fpu_64to (&wop, op);
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boolean = sim_fpu_is_nan (&wop);
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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#ifdef DEBUG
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printf ("DBG: NaN: returning %d for 0x%s (format = %s)\n",
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boolean, pr_addr (op), fpu_format_name (fmt));
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#endif /* DEBUG */
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return (boolean);
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}
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int
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Less (op1, op2, fmt)
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uword64 op1;
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uword64 op2;
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FP_formats fmt;
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{
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int boolean = 0;
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/* Argument checking already performed by the FPCOMPARE code */
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#ifdef DEBUG
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printf ("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",
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fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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boolean = sim_fpu_is_lt (&wop1, &wop2);
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break;
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}
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case fmt_double:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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boolean = sim_fpu_is_lt (&wop1, &wop2);
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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#ifdef DEBUG
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printf ("DBG: Less: returning %d (format = %s)\n",
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boolean, fpu_format_name (fmt));
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#endif /* DEBUG */
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return (boolean);
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}
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int
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Equal (op1, op2, fmt)
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uword64 op1;
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uword64 op2;
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FP_formats fmt;
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{
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int boolean = 0;
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/* Argument checking already performed by the FPCOMPARE code */
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#ifdef DEBUG
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printf ("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",
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fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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boolean = sim_fpu_is_eq (&wop1, &wop2);
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break;
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}
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case fmt_double:
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{
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sim_fpu wop1;
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sim_fpu wop2;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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boolean = sim_fpu_is_eq (&wop1, &wop2);
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break;
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}
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default:
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fprintf (stderr, "Bad switch\n");
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abort ();
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}
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#ifdef DEBUG
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printf ("DBG: Equal: returning %d (format = %s)\n",
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boolean, fpu_format_name (fmt));
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#endif /* DEBUG */
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return (boolean);
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}
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/* Basic arithmetic operations. */
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static unsigned64
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fp_unary(sim_cpu *cpu,
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address_word cia,
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int (*sim_fpu_op)(sim_fpu *, const sim_fpu *),
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unsigned64 op,
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FP_formats fmt)
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{
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sim_fpu wop;
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sim_fpu ans;
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unsigned64 result = 0;
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/* The format type has already been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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unsigned32 res;
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sim_fpu_32to (&wop, op);
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(*sim_fpu_op) (&ans, &wop);
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sim_fpu_to32 (&res, &ans);
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result = res;
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break;
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}
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case fmt_double:
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{
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unsigned64 res;
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sim_fpu_64to (&wop, op);
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(*sim_fpu_op) (&ans, &wop);
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sim_fpu_to64 (&res, &ans);
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result = res;
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break;
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}
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default:
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
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}
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return result;
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}
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|
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static unsigned64
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fp_binary(sim_cpu *cpu,
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address_word cia,
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int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
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unsigned64 op1,
|
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unsigned64 op2,
|
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FP_formats fmt)
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{
|
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sim_fpu wop1;
|
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sim_fpu wop2;
|
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sim_fpu ans;
|
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unsigned64 result = 0;
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|
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/* The format type has already been checked: */
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switch (fmt)
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{
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case fmt_single:
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{
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unsigned32 res;
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sim_fpu_32to (&wop1, op1);
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sim_fpu_32to (&wop2, op2);
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(*sim_fpu_op) (&ans, &wop1, &wop2);
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sim_fpu_to32 (&res, &ans);
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result = res;
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break;
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}
|
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case fmt_double:
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{
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unsigned64 res;
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sim_fpu_64to (&wop1, op1);
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sim_fpu_64to (&wop2, op2);
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(*sim_fpu_op) (&ans, &wop1, &wop2);
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sim_fpu_to64 (&res, &ans);
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result = res;
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break;
|
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}
|
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default:
|
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sim_io_eprintf (SD, "Bad switch\n");
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abort ();
|
|
}
|
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|
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return result;
|
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}
|
|
|
|
|
|
unsigned64
|
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fp_abs(sim_cpu *cpu,
|
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address_word cia,
|
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unsigned64 op,
|
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FP_formats fmt)
|
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{
|
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return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt);
|
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}
|
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|
|
unsigned64
|
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fp_neg(sim_cpu *cpu,
|
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address_word cia,
|
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unsigned64 op,
|
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FP_formats fmt)
|
|
{
|
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return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt);
|
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}
|
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|
|
unsigned64
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fp_add(sim_cpu *cpu,
|
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address_word cia,
|
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unsigned64 op1,
|
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unsigned64 op2,
|
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FP_formats fmt)
|
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{
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return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt);
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}
|
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|
|
unsigned64
|
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fp_sub(sim_cpu *cpu,
|
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address_word cia,
|
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unsigned64 op1,
|
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unsigned64 op2,
|
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FP_formats fmt)
|
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{
|
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return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt);
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}
|
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|
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unsigned64
|
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fp_mul(sim_cpu *cpu,
|
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address_word cia,
|
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unsigned64 op1,
|
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unsigned64 op2,
|
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FP_formats fmt)
|
|
{
|
|
return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt);
|
|
}
|
|
|
|
unsigned64
|
|
fp_div(sim_cpu *cpu,
|
|
address_word cia,
|
|
unsigned64 op1,
|
|
unsigned64 op2,
|
|
FP_formats fmt)
|
|
{
|
|
return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt);
|
|
}
|
|
|
|
unsigned64
|
|
fp_recip(sim_cpu *cpu,
|
|
address_word cia,
|
|
unsigned64 op,
|
|
FP_formats fmt)
|
|
{
|
|
return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt);
|
|
}
|
|
|
|
unsigned64
|
|
fp_sqrt(sim_cpu *cpu,
|
|
address_word cia,
|
|
unsigned64 op,
|
|
FP_formats fmt)
|
|
{
|
|
return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt);
|
|
}
|
|
|
|
|
|
uword64
|
|
convert (sim_cpu *cpu,
|
|
address_word cia,
|
|
int rm,
|
|
uword64 op,
|
|
FP_formats from,
|
|
FP_formats to)
|
|
{
|
|
sim_fpu wop;
|
|
sim_fpu_round round;
|
|
unsigned32 result32;
|
|
unsigned64 result64;
|
|
|
|
#ifdef DEBUG
|
|
#if 0 /* FIXME: doesn't compile */
|
|
printf ("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",
|
|
fpu_rounding_mode_name (rm), pr_addr (op), fpu_format_name (from),
|
|
fpu_format_name (to), pr_addr (IPC));
|
|
#endif
|
|
#endif /* DEBUG */
|
|
|
|
switch (rm)
|
|
{
|
|
case FP_RM_NEAREST:
|
|
/* Round result to nearest representable value. When two
|
|
representable values are equally near, round to the value
|
|
that has a least significant bit of zero (i.e. is even). */
|
|
round = sim_fpu_round_near;
|
|
break;
|
|
case FP_RM_TOZERO:
|
|
/* Round result to the value closest to, and not greater in
|
|
magnitude than, the result. */
|
|
round = sim_fpu_round_zero;
|
|
break;
|
|
case FP_RM_TOPINF:
|
|
/* Round result to the value closest to, and not less than,
|
|
the result. */
|
|
round = sim_fpu_round_up;
|
|
break;
|
|
|
|
case FP_RM_TOMINF:
|
|
/* Round result to the value closest to, and not greater than,
|
|
the result. */
|
|
round = sim_fpu_round_down;
|
|
break;
|
|
default:
|
|
round = 0;
|
|
fprintf (stderr, "Bad switch\n");
|
|
abort ();
|
|
}
|
|
|
|
/* Convert the input to sim_fpu internal format */
|
|
switch (from)
|
|
{
|
|
case fmt_double:
|
|
sim_fpu_64to (&wop, op);
|
|
break;
|
|
case fmt_single:
|
|
sim_fpu_32to (&wop, op);
|
|
break;
|
|
case fmt_word:
|
|
sim_fpu_i32to (&wop, op, round);
|
|
break;
|
|
case fmt_long:
|
|
sim_fpu_i64to (&wop, op, round);
|
|
break;
|
|
default:
|
|
fprintf (stderr, "Bad switch\n");
|
|
abort ();
|
|
}
|
|
|
|
/* Convert sim_fpu format into the output */
|
|
/* The value WOP is converted to the destination format, rounding
|
|
using mode RM. When the destination is a fixed-point format, then
|
|
a source value of Infinity, NaN or one which would round to an
|
|
integer outside the fixed point range then an IEEE Invalid
|
|
Operation condition is raised. */
|
|
switch (to)
|
|
{
|
|
case fmt_single:
|
|
sim_fpu_round_32 (&wop, round, 0);
|
|
sim_fpu_to32 (&result32, &wop);
|
|
result64 = result32;
|
|
break;
|
|
case fmt_double:
|
|
sim_fpu_round_64 (&wop, round, 0);
|
|
sim_fpu_to64 (&result64, &wop);
|
|
break;
|
|
case fmt_word:
|
|
sim_fpu_to32i (&result32, &wop, round);
|
|
result64 = result32;
|
|
break;
|
|
case fmt_long:
|
|
sim_fpu_to64i (&result64, &wop, round);
|
|
break;
|
|
default:
|
|
result64 = 0;
|
|
fprintf (stderr, "Bad switch\n");
|
|
abort ();
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
printf ("DBG: Convert: returning 0x%s (to format = %s)\n",
|
|
pr_addr (result64), fpu_format_name (to));
|
|
#endif /* DEBUG */
|
|
|
|
return (result64);
|
|
}
|
|
|
|
static const char *
|
|
fpu_format_name (FP_formats fmt)
|
|
{
|
|
switch (fmt)
|
|
{
|
|
case fmt_single:
|
|
return "single";
|
|
case fmt_double:
|
|
return "double";
|
|
case fmt_word:
|
|
return "word";
|
|
case fmt_long:
|
|
return "long";
|
|
case fmt_unknown:
|
|
return "<unknown>";
|
|
case fmt_uninterpreted:
|
|
return "<uninterpreted>";
|
|
case fmt_uninterpreted_32:
|
|
return "<uninterpreted_32>";
|
|
case fmt_uninterpreted_64:
|
|
return "<uninterpreted_64>";
|
|
default:
|
|
return "<format error>";
|
|
}
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
static const char *
|
|
fpu_rounding_mode_name (int rm)
|
|
{
|
|
switch (rm)
|
|
{
|
|
case FP_RM_NEAREST:
|
|
return "Round";
|
|
case FP_RM_TOZERO:
|
|
return "Trunc";
|
|
case FP_RM_TOPINF:
|
|
return "Ceil";
|
|
case FP_RM_TOMINF:
|
|
return "Floor";
|
|
default:
|
|
return "<rounding mode error>";
|
|
}
|
|
}
|
|
#endif /* DEBUG */
|